MIPI Clock questions

[titusstalin]

Hello,

Took the below details from page no 2725, Reference manual:

The maximum bandwidth of the interface is as follows:
• 200Mhz for 4 data lanes configuration (800Mbps/lane, 400MByte/sec)
• 187.5Mhz for 3 data lanes configuration (1000Mbps/lane, 375MByte/sec)
• 125Mhz for 2 data lanes configuration (1000Mbps/lane, 250MByte/sec )
• 62.5Mhz for 1 data lane configuration (1000Mbps/lane, 125Mbyte/sec)

Can you please answer the following questions ?

What is all about the 200MHz, 187.5MHz, 125MHz and 62.5MHz clock values ?

Where we can see/get the clock ?

Is it differential lane clock ?

Then what is the clock for OV5640 MIPI camera ?

I've the customized MIPI camera which supports 4 lanes, how can I get the clock range ?

Need to measure the CLK_P and CLK_N pins ?

What is the sensor clock and MIPI lane clock ?

I've got the below details from below imx link.

https://community.nxp.com/docs/DOC-94312 

1. MIPI DPHY clock should match the camera sensor clock, as the sensor  output Differential clock  range is from 80Mhz to 1000Mhz .

Example:

-     mipi_csi2_write(info, 0x00000014, CSI2_PHY_TST_CTRL1);//ov5640 output clk

+    mipi_csi2_write(info, 0x00000044, CSI2_PHY_TST_CTRL1);//Customer camera sensor

Tips:

The range and the exact value when ref_clock is 27M are showed as below:

#define                PLL_CLK  0x32  //783Mhz

                           // clock_range : register value // exact value when ref clock is 27M

                           //  950-1000MHz :0x74   //999Mhz

                           //  900-950Mhz  :0x54   //972Mhz

                           //  850-900Mhz  :0x34   //900Mhz

                           //  800-850MHz  :0x14   //849Mhz

                           //  750-800MHz  :0x32   //783Mhz

                           //  700-750Mhz  :0x12   //750Mzh

                           //  650-700Mhz  :0x30   //699Mhz

                           //  600-650MHz  :0x10   //648Mhz

                           //  550-600MHz  :0x2e   //600Mhz

                           //  500-550Mhz  :0x0e   //549Mhz

                           //  450-500Mhz  :0x2c   //486Mhz

                           //  400-450MHz  :0x0c   //450Mhz

                           //  360-400MHz  :0x4a   //399Mhz

                           //  330-360Mhz  :0x2a   //360Mhz

                           //  300-330Mhz  :0x48   //330Mhz

                           //  270-300MHz  :0x28   //300Mhz

                           //  250-270MHz  :0x08   //270Mhz

                           //  240-250Mhz  :0x46   //249Mhz

                           //  210-240Mhz  :0x26   //240Mhz

                           //  200-210MHz  :0x06   //210Mhz

                           //  180-200MHz  :0x44   //198Mhz

                           //  160-180Mhz  :0x24   //180Mhz

                           //  150-160MHz  :0x04   //159Mhz

                           //  140-150MHz  :0x42   //150Mhz

                          //  125-140MHz  :0x22   //135Mhz

                          //  110-125MHz  :0x02   //123Mhz

                          //  100-110Mhz  :0x40   //108Mhz

                          //  90-100Mhz   :0x20   //99Mhz

                         //  80-90Mhz    :0x00   //90Mhz (default)

What is the reference clock here 27MHz ?

Is it used inside the imx or camera sensor ?

How its derived and its same all the time ?

Thanks for answering the questions.

Regards,

Titus S.

[titusstalin]

I have asked this question to change the clock for higher resolution.

2592x1944@20FPS, but I didn't find any clock settings in driver other than below settings, using the below settings, I was able to get the frames but very less FPS in qv4l2 app.

   mipi_csi2_write(info, 0x00000014, CSI2_PHY_TST_CTRL1);//Customer camera sensor

I have found root cause of the less fps problem.

Its not due to the imx6 host problem but v4l2 GUI applications.

I have measured the interrupt rate and found it fires the interrupt @20FPS but application is not able to do QBUF and DQBUF for the continuous streaming to achieve the higher FPS.

Thus we can close this issue.

Thanks for your support.

Regards,

Titus S.

[igorpadykov]

Hi Titus

p.2725 RM describes CSI perfomance and and for MIPI option
200MHz, 187.5MHz, 125MHz and 62.5MHz are IPU bandwidth requirement
of the interface, that is requirement for IPU hsp_clk clock, given on p.2 Debug
steps for customer MIPI sensor.docx. Please check Figure 19-2. CSI2IPU gasket architecture
i.MX6DQ RM. Measure the CLK_P and CLK_N pins one can with oscilloscope.
27MHz reference clock is described on p.13 AN5305 MIPI CSI2 Peripheral on i.MX6 MPUs
http://www.nxp.com/assets/documents/data/en/application-notes/AN5305.pdf
For description of MIPI lane clock one can google mipi csi-2 specification.

Best regards
igor
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[titusstalin]

Thanks Igor for your reply.

What frequency I should use if I run the below configuration.

4 Lane count, 2592x1944 and RGB888

• 200Mhz for 4 data lanes configuration (800Mbps/lane, 400MByte/sec)

How can I set/use 200MHz clock in MIPI CSI camera ?

Is it byte clock or CSI Lane clock ?

And I need atleast 16FPS for this resolution. What and how can I configure the clock and PHY_TST_CTRL1 register ?

Where (which pin)  I can measure this clock values 200MHz, 187.5MHz, 125MHz and 62.5MHz in OV5640 MIPI camera ?

In other words, some how OV5640 MIPI camera's clock value should be in this range 62.5MHz to 200MHz right ??

What frequency I will get if I measure CLK_P and CLK_N pins of OV5640 MIPI camera if driver used the below settings.

mipi_csi2_write(info, 0x00000014, CSI2_PHY_TST_CTRL1);

Thanks for your help.

I greatly appreciate your help on this.

Thanks again.

[igorpadykov]

Hi Titus

please check description of xx_PIXEL_CLK in
sect.2.3.1. Bandwidth AN5305 and CCM Chapter of RM.
I do not this that it is possible to "measure this clock values 200MHz,
187.5MHz, 125MHz and 62.5MHz".

Best regards
igor