Hi,
I try to use the Marvell Ethernet Phy 88E1510 with iMX6SoloX.
The 25MHz Quartz input of the Phy is wired on iMX ENET1_RX_CLK muxed in REF_CLK_25M to generate 25MHz.
All RGMII signals are wired correctly (TX/RX_Data[0:3], RX_EN, .... ) as done on Sabre Ref board.
After a quick fixup in marvell driver to add tx clock delay (similarly to AR8031 fixup), the Ethernet works fine in 10/100 Mbps Half/Full duplex.
But the Gigabit is not working at all.
Does it need an additional configuration / wire ?
On the Sabre design, it seems that an output clock of the AR8031 is re-injected in iMX SoloX as "REF_CLK_IN".
Is it necessary to make Gigabit working ?
What are GPR1 and Anatop enet PLL configurations in this case ?
Thanks for your help,
Martin
Hello,
Looks like, for RGMII, using external clock is more preferable solution
(as for i.MX6). Please use ENET_REF_CLK for it – as input clock from external
Ethernet PHY. Please use the reference design as an example.
Have a great day,
Yuri
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