Hello!
We are using custom board based on imx8m mini and there was a problem setting the RMII mode.
In u-boot code was edited and 50Mhz ref clock output exist on pad ENET_TD2 (observing it on oscilloscope),
One of U-Boot change:
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
setbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
setup_iomux_fec();
return set_clk_enet(ENET_50MHZ);
}
but during kernel is booting 50Mhz reference clock disappears (observing it on oscilloscope).
I tried to find a dependencies of that behavior:
1. change or remove pinmux settings
2. change fec1 settings and disable it
but there are no dependencies was found.
Device tree code:
fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x1f
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x91
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x23
>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio1 9 0>;
phy-handle = <ðphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
During kernel booting ref clock disappears and link connection between LAN switch and eth PHY losts.
I will be glad for any help.
Thanks in advance.
Hi Ilya
for rmii clock one can look at solution on
https://community.nxp.com/t5/i-MX-Processors/i-MX8MM-RMII-reference-clock/m-p/952927
Best regards
igor