IMX6UL - Max QSPI memory capacity

[dongjianfeng]

Dear All,

The IMX6UL datasheet says the max memory map for QSPI is 256MB.

However, understand that IMX6UL has two QPSI Buses (Bus A and Bus B), each has two chip selects (SS0, SS1). If we configure each QSPI bus as parallel mode, does it mean the total QSPI flash capacity can be extended to 256MB x 2 = 512 MB? Thanks in advance.

[BiyongSUN]

It is linear 256M memory range for serial to linear address.

SPI  is a serial interface device, but QSPI can simulate linear memory.

It is this chip's design, only reserve 256M linear address to QSPI.

[dongjianfeng]

Hi Biyong,

thanks for reply.  So do you mean the max supported QSPI flash size is 256 MB regardess whether to use the parallel mode?

[BiyongSUN]

one use case is to  use QSPI nor to simulate NOR flash to do XIP.

That is the case in i.MXSoloX M4 core XIP running in QSPI nor.

In the i.MX6UL, it should be a normal use by accessing as SPI nor flash.

In this case, you can ingore the memory map, cause it is use the register to access the device by serial interface.

Then memory space is for simulate a linear device space as mentioned before.

You can check the i.MX6SoloX to get some idea about the QSPI.