IMX6Q 3.17 lvds works for a flash

[joshuaclayton]

my lvds flashes for a second (the penguins) then shows nothing.

I have one board where it stays on, but it has other problems. usb doesn't work, for instance.

All boards worked reliably with kernel 3.0.35

My board uses the sharp lq101k1ly04 display.

Implementing lvds support, I have the following devicetree fragment for video

&ldb {

        status = "okay";

        lvds-channel@0 {

                fsl,data-mapping = "spwg";

                fsl,data-width = <18>;

                status = "okay";

                display-timings {

                        native-mode = <&timing0>;

                        timing0: lq101k1ly04 {

                                clock-frequency = <60000000 65000000 80000000>;

                                hactive = <1280>;

                                vactive = <800>;

                                hback-porch = <20>;

                                hfront-porch = <20>;

                                vback-porch = <4>;

                                vfront-porch = <4>;

                                hsync-len = <10>;

                                vsync-len = <4>;

                        }; 

                }; 

        }; 

};

my struct fb_vidmode  setting (which worked) in 3.0.35 was:

{

     .name = "UNIWEST_SHARP",

     .xres = 1280,

     .yres = 800,

     .pixclock = 15384,

     .left_margin = 20,

     .right_margin = 20,

     .upper_margin = 4,

     .lower_margin = 4,

     .hsync_len = 10,

     .vsync_len = 4,

     .sync = 0,

     .vmode = FB_MODE_NONINTERLACED,

     .flag = 0,

}

My timing looks right to me and works in one case.

Could there be something else wrong I am forgetting?

[joshuaclayton · Accepted solution]

Finally got several SoM board to test with.

LVDS works with all the SoM's with a 1.3d revision imx6q, and not with 1.0 revision chips.

Some clock or voltage difference, maybe?

dmesg shows :

  Switching to timer-based delay loop, resolution 333ns

...

CPU identified as i.MX6Q, silicon rev 1.5

vdd1p1: 800 <--> 1375 mV at 1100 mV

vdd3p0: 2800 <--> 3150 mV at 3000 mV

vdd2p5: 2000 <--> 2750 mV at 2400 mV

vddarm: 725 <--> 1450 mV at 1150 mV

vddpu: 725 <--> 1450 mV at 1150 mV

vddsoc: 725 <--> 1450 mV at 1200 mV

on the new chip vs.

Switching to timer-based delay loop, resolution 15ns

...

CPU identified as i.MX6Q, silicon rev 1.0

vdd1p1: 800 <--> 1375 mV at 1100 mV

vdd3p0: 2800 <--> 3150 mV at 3000 mV

vdd2p5: 2000 <--> 2750 mV at 2400 mV

vddarm: 725 <--> 1450 mV at 1100 mV

vddpu: 725 <--> 1450 mV at 1100 mV

vddsoc: 725 <--> 1450 mV at 1200 mV

on the old nonworking  one.

Since the old ones are getting hard to come by, and the new one works, I'm just going to consider the problem solved.