I2C SCL clock frequency issue

[a_rigoli]

Good Morning,

I'm using the Variscite VAR-SOM-SOLO/DUAL System-On-Module with i.MX6Solo processor. I'm using the dev i2c1 serial interface peripheral to communicate with an external sensor. I modified the (attached) device tree file "imx6qdl-var-som.dtsi" (at line 317) in order to have a clock frequency of 100kHz (i also commented out the code portion of i2c1 relative to the MIPI Camera Serial Interface). The communication is working fine without any error (both SDA and SCL lines are activated and the SOM is able to communicate with the sensor), but the actual clock frequency measured with a logic analyzer on the SCL line is slower (around 85kHz). The clock, even if not equal to 100kHz as set in the device tree, is quite stable. However, inside single bytes communications (8 clock pulses + 9th clock pulse for acknowledge) i can sometimes see a couple of clock pulses with slightly different frequency from the main one. On the SCL line the clock frequency is equal to 86.96kHz for the most part of the communication sequence but there are a couple of pulses with frequency equal to 83.33kHz. Clock frequency is never equal to 100kHz.

Is there any reason for such behavior? Do i need to modify other device tree files?
I don't think it is an hardware issue that slows down the actual clock. You may find attached also the schematics relative to the hardware configuration of SDA and SCL line. 

Thanks for your attention. Kind regards.

Alessandro Rigoli

[CarlosCasillas · Accepted solution]

Hi Alessandro,
It may depend of the clock parent that feeds I2C module, and the available divisors (macros implement approximations).
For complementary information, you could refer to chapter 4.6 “Inter-IC (I2C)” of “i.MX Linux Reference Manual”; however, as you are using a 3rd party board, you could consider directly contacting with Variscite (they provide the BSP and Device Tree):

Variscite Support Center - Variscite 

Hope this will be useful for you.
Best regards!
/Carlos
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