I.MX8M Mini LPDDR4 issue at EVK Schematic.

[netchip]

#i.MX8M Mini 

Dear 

I want to design with I.MX8M Mini  also I will utilize EVK B/D for connection LPDDR4.

today, I found some curious point at LPDDR4 part at EVK schematic.

upper picture captured from Mini. and below picture captured 8M evk also.

Can you guide me, I want to design LPDDR4 with MT53D1024M32D4DT-053 WT:D (4GB) base on i.MX8M Mini.

Even though, EVK design with 2GB, NC chipselect pin remain DRAM nCS1B, DRAM nCS1A, so I could design with 4GB.(MT53D1024M32D4DT-053 WT:D ).

But, why A side B side was different when comparing 8M. DDR connection picture.?

Can you support me about this points ASAP?

[Rita_Wang]

This is the block diagram of 2GB LPDDR4.

[Rita_Wang]

We have confirmed it for you that:

There are 2 channels in LPDDR4，the design in 8MM change the all signals between channel A and B for easier routing. It can be support.