I.MX6UL EIM Bus Clock Problem

[X_Figure]

I use the eim bus to communicate with FPGA. I wonder about the waveform of the EIM bus,Why not regular？

And the example is regular!

[Dhruvit]

Hi @X_Figure,

Please mention the configurations that you have used in EIM communication (like synchronous/asynchronous r/w mode, multiplexed  mode, RWSC/WWSC, etc..)

Please provide me with the device node of EIM for further debugging.

Could you please describe how you are implementing code in userspace for EIM transfer?

Thanks & Regards,
Dhruvit.

[X_Figure]

Hi @Dhruvit

Thank you for your reply, I have a product, and need to upgrade from 3.14 kernel to 5.4.47 kernel，Including the EIM peripheral.  #I.mx6ul

Firstly It's works well on the 3.14 kernel. I will show you the device-tree and user space application below.

Device-tree:

weim: weim@021b8000 {
	compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
	reg = <0x021b8000 0x4000>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_EIM>;
};

&weim {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_weim>;
	#address-cells = <2>;
	#size-cells = <1>;
	status = "okay";
	ranges = <0 0 0x50000000 0x02000000>;

	imx-weim@0,0 {
		compatible = "imx-weim";
		reg = <0 0 0x02000000>;
		#address-cells = <1>;
		#size-cells = <1>;
		bank-width = <2>;
		fsl,weim-cs-timing = <0x50CB9     0x1001         0x1F010100 
                    0x00000000     0x1F044040     0x00000000>;
		};
};


pinctrl_weim: weimgrp {
	fsl,pins = <
		MX6UL_PAD_CSI_MCLK__EIM_CS0_B  	    0x10b0
		MX6UL_PAD_CSI_PIXCLK__EIM_OE   	    0x10b0
		MX6UL_PAD_CSI_VSYNC__EIM_RW	    0x10b0	 
		MX6UL_PAD_CSI_HSYNC__GPIO4_IO20     0xb0		   
			
		MX6UL_PAD_LCD_DATA08__EIM_DATA00	0xC9
		MX6UL_PAD_LCD_DATA09__EIM_DATA01	0xC9
		MX6UL_PAD_LCD_DATA10__EIM_DATA02	0xC9
		MX6UL_PAD_LCD_DATA11__EIM_DATA03	0xC9
		MX6UL_PAD_LCD_DATA12__EIM_DATA04	0xC9
		MX6UL_PAD_LCD_DATA13__EIM_DATA05	0xC9
		MX6UL_PAD_LCD_DATA14__EIM_DATA06	0xC9
		MX6UL_PAD_LCD_DATA15__EIM_DATA07	0xC9

	        MX6UL_PAD_LCD_DATA16__EIM_DATA08              	0xC9
		MX6UL_PAD_LCD_DATA17__EIM_DATA09             	0xC9
		MX6UL_PAD_LCD_DATA18__EIM_DATA10          	0xC9
		MX6UL_PAD_LCD_DATA19__EIM_DATA11          	0xC9
		MX6UL_PAD_LCD_DATA20__EIM_DATA12                0xC9
		MX6UL_PAD_LCD_DATA21__EIM_DATA13 		0xC9
		MX6UL_PAD_LCD_DATA22__EIM_DATA14                0xC9
		MX6UL_PAD_LCD_DATA23__EIM_DATA15                0xC9
        >;
};

Applicaton:

#include<stdio.h>
#include<unistd.h>
#include<sys/mman.h>
#include<sys/types.h>
#include<sys/stat.h>
#include<fcntl.h>
#include <string.h>

#define length 0x100000
#define phy_addr 0x50000000

int main()
{
    unsigned char * map_base;
    FILE *f;
    int n, fd;
	
	

    fd = open("/dev/mem", O_RDWR|O_SYNC);
    if (fd == -1)
    {
        return (-1);
    }

    map_base = mmap(NULL, length, PROT_READ|PROT_WRITE, MAP_SHARED, fd, phy_addr);

    if (map_base == 0)
    {
        printf("NULL pointer!\n");
    }
    else
    {
        printf("Successfull!\n");
    }

    unsigned long addr;
    unsigned char content;
    int i = 0;
    int write_length = 16;
    char tmp_val[length] = {0};
    for(i = 0; i < length; i++)
    	tmp_val[i] = i;
	
    tmp_val[0] = 0x7F;
    tmp_val[1] = 0xFF;
    tmp_val[2] = write_length;

 	printf("write addr:%02x%02x\n",tmp_val[0],tmp_val[1]);
	printf("write length = %d:\n",write_length);	
	
	memcpy(map_base, tmp_val, 3 + write_length)  ;//write addr and data
           
	for (i = 0 ;i < write_length; i++)
    {
        printf("%02x ",tmp_val[ i+ 3]);
	if(0 == (i+1)%9)
	printf("\n");
    }
	printf("\n");

    close(fd);

    munmap(map_base, length);

    return (1);
}

Test:

Secondly, I port the code from 3.14 kernel to 5.4.47 kernel. It works wrong in the clock. 

Device-tree:

weim: weim@21b8000 {
	#address-cells = <2>;
	#size-cells = <1>;
	compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
	reg = <0x021b8000 0x4000>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_EIM>;	
	fsl,weim-cs-gpr = <&gpr>;
	status = "disabled";
};

&weim {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_weim>;
	#address-cells = <2>;
	#size-cells = <1>;
	status = "okay";
	ranges = <0 0 0x50000000 0x08000000>;

	imx-weim@0,0 {
		compatible = "imx-weim";
		reg = <0 0 0x02000000>;
		#address-cells = <1>;
		#size-cells = <1>;
		bank-width = <2>;
		fsl,weim-cs-timing = <0x50CB9     0x1001         0x1F010100 
                    0x00000000     0x1F044040     0x00000000>;		
		};
};


pinctrl_weim: weimgrp {
	fsl,pins = <
		MX6UL_PAD_CSI_MCLK__EIM_CS0_B  	0x10b0
		MX6UL_PAD_CSI_PIXCLK__EIM_OE   	0x10b0
		MX6UL_PAD_CSI_VSYNC__EIM_RW		0x10b0	 
		MX6UL_PAD_CSI_HSYNC__GPIO4_IO20     0xb0		  
		
		MX6UL_PAD_LCD_DATA08__EIM_DATA00	0xC9
		MX6UL_PAD_LCD_DATA09__EIM_DATA01	0xC9
		MX6UL_PAD_LCD_DATA10__EIM_DATA02	0xC9
		MX6UL_PAD_LCD_DATA11__EIM_DATA03	0xC9
		MX6UL_PAD_LCD_DATA12__EIM_DATA04	0xC9
		MX6UL_PAD_LCD_DATA13__EIM_DATA05	0xC9
		MX6UL_PAD_LCD_DATA14__EIM_DATA06	0xC9
		MX6UL_PAD_LCD_DATA15__EIM_DATA07	0xC9

		MX6UL_PAD_LCD_DATA16__EIM_DATA08              	0xC9
		MX6UL_PAD_LCD_DATA17__EIM_DATA09             	0xC9
		MX6UL_PAD_LCD_DATA18__EIM_DATA10          		0xC9
		MX6UL_PAD_LCD_DATA19__EIM_DATA11          		0xC9
		MX6UL_PAD_LCD_DATA20__EIM_DATA12                0xC9
		MX6UL_PAD_LCD_DATA21__EIM_DATA13 			0xC9
		MX6UL_PAD_LCD_DATA22__EIM_DATA14                0xC9
		MX6UL_PAD_LCD_DATA23__EIM_DATA15                0xC9
        >;
};

Application:

It's same to 3.14 kernel version.

Test:

The customer logic works normally, but the FPGA cannot recognize it.

Thanks & Regards,
X_Figure

[Dhruvit]

Hi @X_Figure ,

I hope you are doing well.

Please provide me with output of below command and boot logs to cross-check if the clock is properly enabled.

 $ devmem2 0x020C4080

Thanks & Regards,

Dhruvit Vasavda

[X_Figure]

Hi @Dhruvit , 

     I'm looking forward to your reply online, pleaes!

Thanks & Regards,

X_Figure 

[Dhruvit]

Hi @X_Figure 

I am working on this case. Please give me some time to figure out the concrete answer.

Thanks & Regards

Dhruvit Vasavada

[X_Figure]

@Dhruvit  OK, OK!

sorry for the inconvenience caused.

Thanks & Regards

X_Figure 

[X_Figure]

Hi @Dhruvit 

I've been stuck here for a long time, I checked many solutions and confirmed the relevant registers.

Register 0x020C4080 :

Boot logs:

Thank you for your attention, and I will look forward to your reply.

Thanks & Regards,

X_Figure

[Dhruvit · Accepted solution]

Hi @X_Figure 

I hope you are doing well.

From the output, it seems the EIM clock is enabled.

Please make sure that there is not any other difference between 3.14 kernel and 5.4.47 kernel configuration and FPGA setup.

Thanks & Regards

Dhruvit Vasavada