I.MX6Q aboute MIPI lane clk

[richarddestiny]

Hi，ALL

     I see

     Some Experience When Enable MIPI Camera

      my sensor is OV10640，and the lan clk is 800MHZ，it's saied  that  if the clock lane frequency is 128MHz, the clock range should be 250-270MHz because of DDR clock mode, that mean i should set clock range to 1600MHZ? or other clk?

thanks for your reply!

[igorpadykov]

Hi Richard

in case 800MHz  value "0x14" , described in Debug steps for customer

MIPI sensor.docx should be used.

Best regards

igor

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[richarddestiny]

Hi,igorpadykov

    the default  clock set for ov5640 is "0x14",that means ov5640's clock is about 800MHZ ? but I used oscilloscope measured the clock is "160MHZ" when 1280*720  and   "50MHZ" when 640*480 also, i get the register value of MIPI_CSI2_PHY_STATE  is 0x300 when run 0v5640,but  when  run ov10640 in 800MHZ,I get the register value of MIPI_CSI2_PHY_STATE is 0x230, is that  mean the clock have some mistake? 

and I'm not sure the  virtual channl is corrected set,how can i make sure of this?

thanks for your  replay!

[igorpadykov]

If the clocks are not matched, the MX6x MIPI_CSI Error state register MIPI_CSI_ERR1

is not 0, it would be 0x3, “Start of Transmission Error on data lane”.

So when enable new MIPI camera, need to measure the frequency of clock lane, or

calculate from the related sensor register, then configure MPII DPHY clock.

For virtual channel read "Debug steps for customer MIPI sensor.docx " it shows

steps, also configure OV10640. Since its datasheet is not publicly available, it

is not possible to advice you its settings.

[richarddestiny]

Re: imx6q sabre AI board MIPI camera.

there is a sample problem ，The address 0x021DC014 register's bit 8 is different. (this bit Indicates that the clock lane is actively receiving a DDR clock)

how can i  fixed it?