Thank you Luis for your answer,
It works like a charm ! CS Pin is now properly toggled.
However, I still have a problem with the CS handling in the spidev driver. This is my method (SPI interface is configured elsewhere) :
IOBus_Error SPI::message(const unsigned char *txBuffer, unsigned char *rxBuffer, ssize_t &length, long flags) {
IOBus_Error error = IOBus_Error_None;
int status;
if (handle <= 0) openHandle();
// Build transfer
struct spi_ioc_transfer transfer;
memset(&transfer, 0, sizeof(spi_ioc_transfer));
transfer.tx_buf = (unsigned long)&txBuffer[0];
transfer.rx_buf = (unsigned long)&rxBuffer[0];
transfer.len = length;
transfer.delay_usecs = 0;
transfer.speed_hz = configuration.speed;
transfer.bits_per_word = configuration.bits;
transfer.cs_change = flags & SPI_Flag_CSChange;
// Execute transfers
status = ioctl(handle, SPI_IOC_MESSAGE(1), &transfer);
// Check for errors
if ( status < 0) return IOBus_Error_Write;
return IOBus_Error_None;
}
For example, I want to read one byte at the address 0x24 of my device, so my buffers are the following :
txBuffer = {0x24, 0x00}
rxBuffer = {0x00, 0x00}
cs_change is set to 0 and length to 2
When I use my logic analyzer, I can see that the CS line is pulled up between the 0x24 and 0x00 bytes causing my device not to answer.
I then tried to use 16 bits per word in the SPI configuration to keep the CS line low, and it worked. But it is certainly not the way it has to be handled...
I also tried to set cs_change to 1 but it did not change anything on the CS line. And as I am aware of, cs_change must be 0 to let the CS line unselected between transfers.
Here is a capture of the wrong output on my logic analyzer :
And this is a capture of the wanted output using 16 bits per word, we can see that in this case my device correctly answers (0x05 is the value I was waiting for) :
What am I doing wrong ?
-----------------------------------------------------------------------------------------------------------------------------------------------------
Thanks Luis for your help with the device-tree, I will update my previous comment to reflect the configuration you just gave to me.
I still have another questions about the device-tree configuration:
- You are using MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15, is it different from MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 ? From what I see in the pinfunc file, their input_reg and mux_mode are not the same, will it impact the
- Can I use any (free) GPIO as CS pin do I have to use one labeled as ECSPI4_SSx ?
- What does the hexadecimal number after pin declaration means, and how can I determine the right value to use ? (0x10b0, 0x100b1)
Thanks in advance,
Arnaud
