1) Receive the external MCLK via SAIn_MCLK input pad
According to the iMX8MM reference manual, it is possible for both SAI5 and SAI3 to use the MCLK_5 as the master clock if MCLK_5 is fed to the SAI5_MCLK pad and the IOMUXC_GPR registers are configured accordingly. However, I don't see any document/examples about how to configure it correctly. I took a look at the Linux source files (e.g., fsl_sai.c, fsl_sai_sysfs.c), but it seems like such control is not implemented anywhere.
2) Receive the external MCLK via EXT_CLKn pin
Another possibility is to receive the MCLK_5 via EXT_CLK2 pin and distribute internally through the clock tree. But, the EXT_CLK2 pin is not readily accessible on the iMX8MM EVK. Also, it is less preferreable than the prior method of using the IOMUXC_GPR registers becuase we plan to involve additional SAI for our end appliaction. While the EXT_CLKn is shared between subset of SAIs, the IOMUXC_GPR-based method allows a complete flexibility in choosing the MCLK source.
[ Questions ]
Q1. So far, I was able to customize the kernel using 'simple-audio-card' to record (i.e., arecord) the audio stream coming from the wireless IC. However, I used the IMX8MM_AUDIO_PLL1_OUT as the MCLK. How can I use the MCLK_5 on SAI5_MCLK pad as the master clock? (FYI, the following is my device tree snippet).
/dts-v1/;
#include "imx8mm-evk.dts"
/ {
// wac: wireless audio codec
wac: wac {
#sound-dai-cells = <0>;
compatible = "test,wac";
status = "okay";
};
sound-wac {
compatible = "simple-audio-card";
simple-audio-card,name = "wac";
simple-audio-card,dai-link@0 {
format = "i2s";
bitclock-master = <&wac_dai>;
frame-master = <&wac_dai>;
wac_cpu: cpu {
sound-dai = <&sai5>;
};
wac_dai: codec {
sound-dai = <&wac>;
};
};
};
};
&sai5 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai5>;
assigned-clocks = <&clk IMX8MM_CLK_SAI5>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <1536000>;
status = "okay";
};
&iomuxc {
pinctrl_sai5: sai5grp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6
MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
>;
};
};
Q2. Once the Question 1 has been addressed, how and where can I configure the IOMUXC_GPR registers to use SAI5_MCLK (i.e., MCLK_5) as the master clock for the SAI3?
Q3. In another thread, it says that the system hangs during the boot if a clock is not present on EXT_CLKn pin. Is it the expected behavior? In other words, should the MCLK_5 be available before the system boot and be always present?
Q4. I wonder if the same or similar issue as Q3 is also present in the case of using the SAIn_MCLK pad to feed the external clock. Does MCLK_5 have to be present all the time before the system boot and while the system is operating?
Q5. Continued from Q4, what happens if we activate SAI3 (e.g., aplay) while MCLK_5 is not present?
Thanks,
Woosuk
