How is the MIPI_CSI IP core clocked (on i.MX8M Mini) ?

[laurent_pinchar]

Hello,

I'm trying to bring up camera support on an i.MX8M Mini board with an ON Semiconductor MT9M114 camera sensor. I'm facing a number of different problems, which I'm bringing up in different threads to keep the discussion flow focussed and readable.

The issue here is related to the clocks for the MIPI CSI core, on the i.MX8M Mini. The reference manual lists three input clocks to the MIPI CSI:

• i_RxByteClkHS%, the byte clock derived from the CSI-2 input clock
• I_PCLK, also called the APB clock
• I_ACLK, also called the pixel clock

There are three clock domains (figures 13-26 and  13-44):

• The BCLK clock domain, for the logic connected to the D-PHY. It is clocked by the i_RxByteClkHS% clock.
• The APB clock domain, for the MIPI_CSI registers, clocked by I_PCLK.
• The ACLK clock domain, for the logic connected to the CSI Bridge.

The imx8mm.dtsi device tree in the imx_5.4.70_2.3.0 kernel branch sets the clock to the MIPI CSI as follows:

mipi_csi_1: mipi_csi@32e30000 {
        compatible = "fsl,imx8mm-mipi-csi";
        reg = <0x32e30000 0x1000>;
        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
        clock-frequency = <333000000>;
        clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
                <&clk IMX8MM_CLK_CSI1_PHY_REF>,
                <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
                <&clk IMX8MM_CLK_DISP_APB_ROOT>;
        clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb"; 
        bus-width = <4>;        
        power-domains = <&mipi_pd>;
        status = "disabled";    
};

I believe that `mipi_clk` corresponds to the I_ACLK clock, and `disp_apb` to the I_PCLK clock.

First questions:

• Is this correct ?
• What are the `phy_clk` and `disp_apb` clocks used for, and what are the constraints on their frequencies ?

In the i.MX7D, which has an older version of the MIPI CSI (v3.3), I_ACLK was called I_WRAP_CLK, and the logic connected to the CSI Bridge was clocked by either I_PCLK or I_WRAP_CLK. The clock source was selected by the `WCLK_SRC` field in the `MIPI_CSI2_CSIS_CLK_CTRL` register. On i.MX8MM, the `WCLK_SRC` field is not documented in `MIPI_CSI2_CSIS_CLK_CTRL`, and the corresponding bits are marked as reserved. Still, both the drivers/media/platform/mxc/capture/mxc_mipi_csi.c and the drivers/staging/media/imx/imx8-mipi-csi2-sam.c drivers set the `WCLK_SRC` field to 1 when the `csis-wclk` property is set in the device tree. Experimenting with the driver, setting `WCLK_SRC` to 1 changes the behaviour of the image capture, and thus hints that the field actually exists in the i.MX8MM.

Second questions:

• Can the source of the ACLK clock domain be selected on i.MX8MM ?
• If the source can be selected, is it through the `WCLK_SRC` field (the reference manual would thus be incorrect in documenting that field as reserved), or through a different means ?
• If the source cannot be selected, is it always I_ACLK, or is it another clock ?

[刘国华]

Hi 

Do you have already porting the MT9M114 to the I.MX8M mini successuflly ? I encounter some issue base on I.MX8M nano , Coud you help give some suggestion ?

https://community.nxp.com/t5/i-MX-Processors/Cannot-capture-image-for-SGRBG8-1X8-format-with-On-semi...