ERR007117: Which i.MX devices require gating the clocks when changing ENFC dividers

[ceggers]

ERR007117 in IMX6DQCE.pdf has been fixed in newer boot roms, but the requirements for the application code are still needed:

For other occurrences in application code, the following procedure should be followed to change the clock configuration for the enfc_clk_root:
1) Gate (disable) the GPMI/BCH clocks in register CCM_CCGR4.
2) Gate (disable) the enfc_clk_root before changing the enfc_clk_root source or dividers by clearing CCM_CCGR2[CG7] to 2’b00. This disables the iomux_ipt_clk_io_clk.
3) Configure CCM_CS2CDR for the new clock source configuration.
4) Enable enfc_clk_root by setting CCM_CCGR2[CG7] to 2’b11. This enables the iomux_ipt_clk_io_clk.
5) Enable the GPMI/BCH clocks in register CCM_CCGR4

I recognized that this sequence is also required on i.MX6 ULL (see discussion on GPMI iMX6ull timeout on DMA on linux-mtd list).

Questions:

1. Which i.MX models / series require this sequence?
2. Where can I find this sequence in the reference manuals (e.g. for i.MX6 ULL)?
3. How is CCM_CCGR2[CG7] (iomux_ipt_clk_io_clk) related to "gating enfc_clk_root"?

regards,
Christian

[ceggers]

As I don't expect to get further input from NXP here, it seems that I have to answer this question myself:

1. Which i.MX models / series require this sequence?

According to their reference manuals, the i.MX7 and i.MX8 series contain "synchronized clock dividers" which allow to switch between different divisors without gating the clock. The i.MX6 manual is quiet about this, so most likely this series uses non-synchronized dividers.

2. Where can I find this sequence in the reference manuals (e.g. for i.MX6 ULL)?

It seems that there is no information about this in the manuals.

3. How is CCM_CCGR2[CG7] (iomux_ipt_clk_io_clk) related to "gating enfc_clk_root"?

On the original i.MX6 series (Solo/Dual/Quad), the output clock of the ENFC dividers also supplies the IOMUXC (iomux_ipt_clk_io_clk). Although this clock seems not to be really required for IOMUXC operation [1], it may be a good idea also to gate this clock before changing the ENFC dividers.

On i.MX6ULL, the IOMUXC clocks are not derived from ENFC_CLK_ROOT anymore.

Additional information:

I am quite convinced that the instructions from the Errata are more comprehensive than necessary. For the NAND flash, only the I/O clock is derived from ENFC_CLK_ROOT. All other NAND/BCH related clocks are derived from other sources. So there should be no need to gate them.

Linux kernel status:

Patches for the clock dividers are currently in linux-mtd. I hope that they will get into 5.16 soon and than be merged into the -stable trees.

[1] iomux_ipt_clk_io_clk is not prepared/enabled by any Linux driver. As a consequence, it will be disabled shortly after boot by clk_disable_unused.

[AldoG]

Hello,

1 > As far as I'm aware the impacted chips are the ones mentioned in the errata.

2 > In our Linux BSP it will always gate the clocks before setting it. It is the normal operation code for all clocks, not only for NAND clock.

3 > ENFC_CLK_ROOT is controlled by CG bits in the IOMUXC and GPMI Modules.

Best regards,
Aldo.

[ceggers]

Hi Aldo,

thanks for working on my question.

1. As far as I'm aware the impacted chips are the ones mentioned in the errata.

I am affected by clock glitches on i.MX6ULL. This chip is not mentioned in the errata.

2. In our Linux BSP it will always gate the clocks before setting it. It is the normal operation code for all clocks, not only for NAND clock.

There are two locations in the NAND driver where the clock is set:

1. https://github.com/Freescale/linux-fslc/blob/5.10.x%2Bfslc/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand....
2. https://github.com/Freescale/linux-fslc/blob/5.10.x%2Bfslc/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand....

I cannot see that the clock is gated before being set. Does this happen somewhere else (e.g. in the clock framework)?

3. ENFC_CLK_ROOT is controlled by CG bits in the IOMUXC and GPMI Modules.

Can you please show me the CG bits within the IOMUXC and GPMI modules? Usually the CG bits are located in the CCM modules.

regards
Christian

[ceggers]

@igorpadykov: It seems that I will not get an answer here. Is there another support contact I can use? Can you forward my question to your hardware team?

regards,
Christian