Hello,
We use EIM to write and read a SRAM in asynchronous mode ,where i could able to read and write with the configuration below in IMX6Q.
EIM_CS0GCR1 = 0x00010081
EIM_CS0GCR2 = 0x00000000
EIM_CS0RCR1 = 0x04000000
EIM_CS0RCR2 = 0x00000000
EIM_CS0WCR1= 0x04000000
EIM_CS0WCR2= 0x00000000
where read and write able to do in 30 ns and the turn around time in between is 270 ns.
1. I need to reduce the turn around time less than 40 ns could it be acheivable ?
2. where I need to change the configuration and things to taken care to acheive write and read with turn around time less than 100 ns?
thanks in advance ..
uday
Your current EIM setup already implements the fastest turnaround time of the accesses. So, most likely, the large gaps between the accesses are caused by the processor's internal buses arbitration timings and cannot be improved.
Have a great day,
Artur
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Hi Artur,
Is this turnaround time coming into play when performing a because Udaya seems to be doing alternate Write and Read?
What if I am doing consecutive Writes? I am facing a similar issue, I am using a 16 bit multiplexed Asynchronous mode. And from my code I am writing 32 bytes of data in a for loop. I am using iMX51 though but I guess the symptom is the same. Here is my WEIM CS0 configuration:
{
0x00010039 , //CSxGCR1
0x00000002 , //CSxGCR2
0x20475230 , //CSxRCR1
0x00000000 , //CSxRCR2
0x609C0E98 , //CSxWCR1
0x00000000 , //CSxWCR2
}
I am able to increase/decrease the CS timing using CS0WCR1.WWSC but the delay in between two consecutive chip selects is of the order of 200nanoSecs, even though I have set CS0GCR1.CSREC to 0.
The rate at which I can send data out on the WEIM Bus is very critical, can you please suggest me a way in which the inter-CS time can be brought down? Is Burst mode synchronous access going to result in faster data throughput?