Does the i.MX7D's EIM bus support 8-bit muxed mode?

[dan_griscom]

I'm using an i.MX7D's EIM bus to communicate with an FPGA. I have EIM_AD00 through EIM_AD09 connected, and was going to configure the EIM as a multiplexed address/data bus (EIM_CS0GCR1:MUM == 1), with the data in the bottom 8 bits of the bus (EIM_CS0GCR1:DSZ == 0x4) in asynchronous mode (EIM_CS0GCR1:SRD == 0 and EIM_CS0GCR1:SWR == 0).

Problem: no matter what I do, the data I read from the bus is all 0s. After much thrashing around, on a lark I tried setting DSZ to 32-bit mode (DSZ == 0x3). Bingo: the bottom 8 bits now show the expected data. So, now I'm wondering if 8-bit multiplexed mode is supported. Looking at the spec sheet and reference manual, I see contradictory statements; sometimes they state or imply that it is, sometimes they state or imply that it isn't. I also tried 16-bit MUXed mode using the low bits of the bus(DSZ == 0x1), and that worked, with the data showing up in the low byte. Strangely, I also got the same results when I set up 16-bit mode using the high bits of the bus (DSZ == 0x2).

Does the i.MX7D's EIM bus support 8-bit multiplexed address/data mode? And, does it make sense that in multiplexed mode DSZ == 0x1 and DSZ == 0x2 give the same results?

(BTW, here's the contents of /proc/cpuinfo:

processor : 0

model name : ARMv7 Processor rev 5 (v7l)

BogoMIPS : 16.00

Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm

CPU implementer : 0x41

CPU architecture: 7

CPU variant : 0x0

CPU part : 0xc07

CPU revision : 5

processor : 1

model name : ARMv7 Processor rev 5 (v7l)

BogoMIPS : 16.00

Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm

CPU implementer : 0x41

CPU architecture: 7

CPU variant : 0x0

CPU part : 0xc07

CPU revision : 5

Hardware : Freescale i.MX7 Dual (Device Tree)

Revision : 0000

Serial : 0000000000000000

)

[igorpadykov · Accepted solution]

Hi Daniel

it is not supported as described in Table 44. EIM internal module multiplexing

i.MX7D Datasheet

http://cache.nxp.com/files/32bit/doc/data_sheet/IMX7DCEC.pdf

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[x10]

IMX7D EIM can work as 8-bit mux mode with config AD[0..7] pins, and ignore high byte data. 

BR

Cheng Shi

[dan_griscom]

I'd seen that, but the text is unfortunately unclear that the displayed modes are the only allowed modes (e.g. the table does not include non-multiplexed DSZ values of 110b and 111b, even though those are explicitly allowed in the reference manual).

Thanks,
Dan

[igorpadykov]

reference manual gives general description of IP EIM module, particular

implementation may be different on different chips, which is described in

datasheet for particular processor.

Best regards
igor

[dan_griscom]

Understood, but even the datasheet isn't clear.

Such is life,

Dan