Hello,
I am trying to implement 4GB DDR3 for i.MX6Q. Depending on the Hardware Development Guide, T topology design is limited to 4 DDR chips.
> -your design is limited to 4 DDR chips.
> -DDR3, 2GByte using latest memories (4GBytes coming) (<- Is this really "Byte" ? or "2Gbit / chip"?)
Does it mean that only Fly-by topology can achieve 4GByte configuration?
AW designer says that it's hard to achieve the layout requirement of Fly-by topology with 8 of DDR3 chips and they want to use T-topology.
Thank you.
已解决! 转到解答。
According to the i.MX6 design Checklist, it is suggested to use "T" topology
when the number of DDR3 chips are not more than four. Otherwise "Fly-by"
Topology is recommended, since it allows to decrease timing / trace length
requirements because of additional calibration procedures.
According to the i.MX6 design Checklist, it is suggested to use "T" topology
when the number of DDR3 chips are not more than four. Otherwise "Fly-by"
Topology is recommended, since it allows to decrease timing / trace length
requirements because of additional calibration procedures.