DQS-DQ skew with LPDDR4 in i.MX93EVK

[TTamura_Apollo_Giken]

Hello.
I am in charge of transmission line simulation at a board design company.

I was asked by a customer to start a board design using i.MX93 and I used the HyperLynx DDRx batch wizard to analyze LPDDR4 using i.MX93EVK board data.

The IBIS model for the DRAM was MT53E1G16D1ZW from z42n_1p1v_at.ibs referring to the i.MX93EVK schematic, and the observation points were performed on the die.

Looking at the analysis results without leveling, it seems that the DQS-DQ skew is way off and there is little margin on the Hold side.

The hardware guide describes routing constraints for delay time, but are these constraints specified as the range of phase adjustment based on the assumption of delay and leveling operation in the package on the DRAM side?
Is the range that can be adjusted by leveling described anywhere?

The attached image is the result of HyperLynx analysis and the eye mask is the default setting of HyperLynx, not the i.MX93 specification

[pengyong_zhang · Accepted solution]

Hi, @TTamura_Apollo_Giken 

Our EVK PCB design has been proven, So if you have following the HDG file, then your board is no problem. And you can use the Config Tool run the vTSA test.

B.R

[pengyong_zhang]

Hi, @TTamura_Apollo_Giken 

>>>Is it assumed that even if there is a phase difference (wire length difference) between DQS and DQ in i.MX93EVK, it will be adjusted by leveling?

Yes!

>>>the i.MX93 package delay and PCB routing delay alone are specified, but does this mean that the specified values are such that problems do not occur without considering the DRAM package delay?

It is the design range, The DDR training will calibration the DQS2DQ, and this is fine-tuned and must be based on meeting the PCB design.

[TTamura_Apollo_Giken]

Hi @pengyong_zhang 
Thanks for the reply.
Is it your understanding that as a device manufacturer, you guarantee operation by following the hardware design guide and matching the delay time of the PCB wiring design?
In the simulation, is it enough to confirm that the adjusted time is within the leveling range by performing Write leveling, and that the i.MX93 eye mask regulations are satisfied as signal quality?

[TTamura_Apollo_Giken]

Hi

JEDEC 209-4B confirmed.
LPDDR4-3200 read as follows
TdIVW_total max:0.25UI
tDQS2DQ min:200ps / max:800ps
tDQ2DQ max:30ps

Is it assumed that even if there is a phase difference (wire length difference) between DQS and DQ in i.MX93EVK, it will be adjusted by leveling?

Also, the i.MX93 package delay and PCB routing delay alone are specified, but does this mean that the specified values are such that problems do not occur without considering the DRAM package delay?

[pengyong_zhang]

Hi, @TTamura_Apollo_Giken 

Different DDR type have different Spec document, For i.MX93 LPDDR4, you can refer JEDE209-4C.

B.R

[TTamura_Apollo_Giken]

Hi
We were aware that the range that can be supported by leveling depends on the DDR controller.
Also, the JEDEC standard is a specification for the DRAM side, so we do not know the specifications for the controller side.
The old i.MX6 datasheet included DDR2/3 timing specifications, but the recent DDR timing specifications are not included, so we do not know the controller specifications.

[pengyong_zhang]

Hi, @TTamura_Apollo_Giken 

About all of the DRAM range that can be adjusted by leveling, you can find it on JEDEC spc document.

B.R

[TTamura_Apollo_Giken]

Hi @pengyong_zhang 
JEDEC 209-4B confirmed.
LPDDR4-3200 read as follows
TdIVW_total max:0.25UI
tDQS2DQ min:200ps / max:800ps
tDQ2DQ max:30ps

Is it assumed that even if there is a phase difference (wire length difference) between DQS and DQ in i.MX93EVK, it will be adjusted by leveling?

Also, the i.MX93 package delay and PCB routing delay alone are specified, but does this mean that the specified values are such that problems do not occur without considering the DRAM package delay?

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