Confused about DDR frequency in i.MX6 Solo

[fmvalero]

Hi all,

I've read several posts about DDR frequency, but there is one thing I don't understand. If I'm not wrong, the DDR clock is the clock named as MMDC_CH0_CLK_ROOT in the reference manual. The DDR clock frequency must be 400 MHz for the i.MX6 Solo processor. However, according to the reference manual, the default frequency for MMDC_CH0_CLK_ROOT is 528 MHz. I've used the DDR3 Script Aid to configure the DDR3 initialization, but I don't see at any time that CBCMR register is written for selecting PFD2 396 as clock source for MMDC_CH0_CLK_ROOT. So, I assume that if clock source is not changed, the DDR clock will be running at the default value (528 MHz), although the script is done for 400 MHz.

Also, I've been viewing other boards (e. g. Nitrogen6x) that have a DDR configuration file in u-boot done for i.MX6 Solo, and the change of clock source is never made. So, how is possible that DDR clock is running at 400 MHz?

Any clarification here, please? Thanks.

[fmvalero]

OK. Thank you for your reply.

[art · Accepted solution]

You are right in that, with the default settings, the MMDC_CH0_CLK_ROOT clock is running at 528MHz. Its switching to 400MHz, required for normal i.MX6Solo operation, is performed as the part of the global configuration procedure of the Clock Controller Module (CCM), that is performed at the early boot stage, when the boot ROM code is processing the Device Configuration Data (DCD) structure of the boot image.

Have a great day,
Artur

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------