Configuring mmdc io on imx6sll for self-refresh mode

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Configuring mmdc io on imx6sll for self-refresh mode

Contributor I

Hi All,

I'm trying to add self-refresh mode support for lpddr2 on imx6sll. I was able to establish an approximate list of "mmdc" registers,

static const u32 imx6sll_mmdc_lpddr2_offset[] __initconst = {
    0x01c, 0x800, 0x85c, 0x890,     /*MDSCR,MPZQHWCTRL,MPZQLP2CTL,MPPDCMPR2*/
    0x8b8, 0x81c, 0x820, 0x824,     /*MPMUR0,MPRDDQBY0DL,MPRDDQBY1DL,MPRDDQBY2DL*/
    0x828, 0x82c, 0x830, 0x834,     /*MPRDDQBY3DL,MPWRDQBY0DL,MPWRDQBY1DL,MPWRDQBY2DL*/
    0x838, 0x83c, 0x848, 0x850,     /*MPWRDQBY3DL,MPDGCTRL0,MPRDDLCTL,MPWRDLCTL*/
    0x8c0, 0x8b8, 0x004, 0x00c,        /*MPDCCR,MPMUR0,MDPDC,MDCFG0*/
    0x010, 0x038, 0x014, 0x018,      /*MDCFG1,MDCFG3LP,MDCFG2,MDMISC*/
    0x01c, 0x02c, 0x030,             /*MDSCR,MDRWD,MDOR*/
    0x040, 0x000, 0x020,             /*MDASP,MDCTL,MDREF*/
    0x800, 0x004, 0x01c,            /*MPZQHWCTRL,MDPDC,MDSCR*/

thanks to a reference manual, and values for some of them,

        pm_info->mmdc_val[0][1] = 0x8000;
        pm_info->mmdc_val[1][1] = 0xa1390003;
        pm_info->mmdc_val[3][1] = 0x400000;
        pm_info->mmdc_val[4][1] = 0x800;
        pm_info->mmdc_val[17][1] = 0x800;
        pm_info->mmdc_val[18][1] = 0x20024;
        pm_info->mmdc_val[23][1] = 0x201708;
        pm_info->mmdc_val[24][1] = 0x8000;
        pm_info->mmdc_val[30][1] = 0xa1310003;

but I can not find any information about the list of "mmdc io" registers for imx6sll. All this is complicated by the fact that in imx6sll there are no "mmdc io" registers (CAS, RAS, SODT0, SODT1, DRAM_RESET), and because of this I can not make simple mapping of registers from another processor, such as imx6sl or imx6sx.

Can anyone tell me which "mmdc io" registers I need to save, or is it possible for someone to have documentation on this topic for imx6sll?

Thanks & Regards,


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NXP TechSupport
NXP TechSupport

Hi Valentin

sect.27.10 MMDC Memory Map/Register Definition i.MX6SLL Reference Manual

describes all MMDC addresses 

I believe there is some misunderstaning since i.MX6SLL does not support DDR3 so

some features may be absent (there are no CAS, RAS, SODT0, SODT1, DRAM_RESET signals).

Best regards
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