On the I.MX6UL scheme，in order to make CCM_CLK1_N/P output 66MHz clock, now set the PMU_MISC1N:LVDS1_CLK_SEL source to PFD6 -- REF_PFD6_CLK == PLL2_PFD2_CLK. When set, there is no clock output.
The schematic diagram is as follows（See the attachment）:
The application is as follows:
// IPG_CLK_ROOT
// 1. CBCMR:PRE_PERIPH_CLK_SEL(01 derive clock from PLL2 PFD2)
cbcmr_map = (volatile unsigned char *)mmap(NULL, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x20C4000);
cbcmr_pre_periph_clk_sel = (volatile unsigned int *)(cbcmr_map + 0x18);
*cbcmr_pre_periph_clk_sel = (1 << 18); // 396Mhz
// 2. CBCDR:PRE_PERIPH_CLK_SEL(0 PLL2 (pll2_main_clk))
cbcdr_pre_periph_clk_sel = (volatile unsigned int *)(cbcmr_map + 0x14);
*cbcdr_pre_periph_clk_sel = (0 << 26); // 396Mhz
// 3. AHB_CLK_ROOT,CBCDR:AHB_PODF (010 Divide by 3)
*cbcdr_pre_periph_clk_sel = *cbcdr_pre_periph_clk_sel|(2 << 10); // 132Mhz
// 4. IPG_CLK_ROOT :CBCDR:IPG_PODF (01 divide by 2)
*cbcdr_pre_periph_clk_sel = *cbcdr_pre_periph_clk_sel|(1 << 8); // 66Mhz
// 5. set CCM_CLK1_N/P
// PMU_MISC1N:LVDS1_CLK_SEL (PFD6 — ref_pfd6_clk == pll2_pfd2_clk)
ccm_clk_p_n = (volatile unsigned int *)(pmu_misc1n_map + 0x160);
*ccm_clk_p_n = (0x4 << 0); // CCM_CLK1_N/P ouput clk 66Mhz
Please check whether this setup is feasible. How does it need to be modified? Thank you
