About MMDC PHY Read DQS Gating Control Register in i.MX6DQ.

[keitanagashima]

Dear All,

I have a question about DDR setting register.

My customer would like to use DDR3_x64.

Refer to 44.12.46 MMDC PHY Read DQS Gating Control Register 0 (MMDCx_MPDGCTRL0) in MCIMX6DQRM(Rev.2).

There is below description.

======

For Channel 0: DDR3_x16, DDR3_x32, DDR3_x64

For Channel 1: DDR3_x64

======

Next, refer to "DG_HC_DEL1" bits.

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Read DQS gating half cycles delay for Byte1 (channel 0 register) and Byte5 in 64-bit mode (channel 1 register)

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Last, refer to "DG_CMP_CYC" and "DG_DIS" bit ,etc.

There isn't the description of channel 0 and channel 1.

[Question]

How should one set channel 0 and channel 1 to MMDCx_MPDGCTRL0?

I couldn't understand well...

Best Regards,

Keita

[igorpadykov]

Hi Keita

DQS Gating is used only for DDR3 memory, only channel 0 is used.

I.MX6Q has two “logic controllers” – one controller for each “channel”

or AXI port - this is not relevant for DDR3, only for LPDDR2.

Channel 1 ‘logic controller’ only employed when configuring MMDC for

dual-channel LPDDR2 usage and not used for DDR3.

Best regards

igor

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[keitanagashima]

Hi Igor,

Thank you for your reply.

Sorry, I couldn't understand well.

Let me clarify these registers again.

My customer will use DDR3 with x64 bits width.

Refer to 44.12.46 MMDC PHY Read DQS Gating Control Register 0 (MMDCx_MPDGCTRL0) in MCIMX6DQRM(Rev.2).

Are these below description typo??

1. Supported Mode Of Operations:

======

For Channel 0: DDR3_x16, DDR3_x32, DDR3_x64

For Channel 1: DDR3_x64

======

2. DG_HC_DEL1 and DG_HC_DEL0 bits

======

Read DQS gating half cycles delay for Byte1 (channel 0 register) and Byte4 in 64-bit mode (Channel 1 register)

======

Best Regards,

Keita

[igorpadykov]

Hi Keita,

sorry, I couldn't understand well:

where so you think typo - what word exactly?

Best regards

igor

[keitanagashima]

Hi Igor,

You answered; DQS Gating is used only for DDR3 memory, only channel 0 is used.

So I consider that below description looks typo.

1. Supported Mode Of Operations:

======

For Channel 0: DDR3_x16, DDR3_x32, DDR3_x64

For Channel 1: DDR3_x64

======

2. DG_HC_DEL1 and DG_HC_DEL0 bits

======

Read DQS gating half cycles delay for Byte1 (channel 0 register) and Byte4 in 64-bit mode (Channel 1 register)

======

Best Regards,

Keita

[igorpadykov]

Hi Keita,

thanks for clarifcation.

This is not accurate wording, since there are

two logic terms (please look at image above):

1. Channel1 logic controller

2. Channel1 PHY

meaning in text was for "Channel1 PHY" - configuration

characteristics for data bytes [4-7]

Best regards

igor

[keitanagashima]

Hi Igor,

Thank you for your reply.

i.e. DG_HC_DEL1 and DG_HC_DEL0 bits were set for Channel 0 & 1 PHY?

Refer to Figure 2. DDR3 64-Bit Calibration Registers in AN4476(Rev.2).

I have understood that MMDCx_MPDGCTRL0 register is "Calibration control" which is in Figure.2.

Best Regards,

Keita

[igorpadykov · Accepted solution]

Hi Keita,

>DG_HC_DEL1 and DG_HC_DEL0 bits were set for Channel 0 & 1 PHY?

Yes.

>Refer to Figure 2. DDR3 64-Bit Calibration Registers in AN4476(Rev.2).

>I have understood that MMDCx_MPDGCTRL0 register is "Calibration control" which is in Figure.2.

I think Figure 2 just shows generic structure, not registers.

Best regards

igor