About IMX8QM-MEK MAX9286-GMSL

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About IMX8QM-MEK MAX9286-GMSL

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zhoubingying1012
Contributor I

We try to use GMSL(max9286_+max9271+OV10635) on imx8qm board with the default BSP. All the the boards(IMX8qm,max9286, max9271 and OV10635) is designed by ourself. The IIC communication between imx8qm, max9286, max9271 and OV10635 is right, but GMSL is not work. With deep trace, I find I can not write ox0f to the reg 0x0100 of OV10635 after write ox10 to the reg 0x3023 of OV10635. Can you give me some suggest or some reference?

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zhoubingying1012
Contributor I

The schematic as shown below:

zhoubingying1012_1-1689297601587.png

 

zhoubingying1012_0-1689297207178.png

the device tree node:

*/

&i2c_mipi_csi0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c_mipi_csi0>;
//clock-frequency = <100000>; //dleted by zhoubingying
clock-frequency = <50000>;
status = "okay";

max9286_mipi@6a {
compatible = "maxim,max9286_mipi";
reg = <0x6a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mipi_csi0>;
clocks = <&clk_dummy>;
clock-names = "capture_mclk";
mclk = <27000000>;
mclk_source = <0>;
pwn-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_HIGH>;
en-gpios = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>;
virtual-channel;
status = "okay";
port {
max9286_0_ep: endpoint {
remote-endpoint = <&mipi_csi0_ep>;
data-lanes = <1 2 3 4>;
};
};
};
};

/* MIPI RX */
&isi_6 {
interface = <2 0 2>; /* <Input MIPI_VCx Output>
Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM
VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only
Output: 0-DC0, 1-DC1, 2-MEM */
status = "okay";
cap_device {
status = "okay";
};
};

I use gmsl-max9286.c as driver in kernel,All the IIC communication is OK。 I can not write ox0f to the reg 0x0100 of OV10635 after writting oxF0 to the reg 0x3023 of OV10635 and can't capture the video from camera.

 

 

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Dhruvit
NXP TechSupport
NXP TechSupport

Hi @zhoubingying1012,

I hope you are doing well.

Please make sure device tree nodes and pin connections for GMSL and OV10635.

Bit 4 of 0x3023 SC_CMMN_CORE_CTRL[4] register is Clock switch configuration pin.

0: Switch all clock to pad
clock
1: Switch from pad clock to
all clock

and  0x0100 STREAM MODE register is used to on the stream in OV10635.

Please provide me with the device tree and schematic of connections for further debugging.

Thanks & Regards,
Dhruvit Vasavada

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