4 chips DDR3 and hybrid topology

[massimo2]

Hello

I would like to improve my project.
If i have 4 x DDR3 chips on the same layer(top or bottom). From now i will call them "M" with a number.
May i crate an hybrid topology between T and fly-by using chip selects and multiple clocks?
Like
M1-M2 use CLK0 diff signal, CS0  data D[0-31]
&
M3-M4
use CLK1,CS1 and data D[32-63].
May i do that or i'm forced to use only first 32bits(data)?

The address lines could divide in 2 between 2 memory group like the T topology, like they are routed between M2 and M3 and then split.
  .--------------MPU----------.
 ck0            ||||addr       ck1
|M1||M2| <=====> |M3||M4|

[igorpadykov]

Hi Massimo

>May i crate an hybrid topology between T and fly-by using chip selects and multiple clocks?

sorry this is not recommended.

>M3-M4 use CLK1,CS1 and data D[32-63].
>May i do that or i'm forced to use only first 32bits(data)?

MMDC allows only first 32bits(data) as described in

sect.44.12.1 MMDC Core Control Register (MMDCx_MDCTL) for "DSIZ" field

i.MX 6Dual/6Quad Applications Processor Reference Manual

Best regards
igor
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[massimo2]

Thank you.