I'm looking for timing constraints for routing discrete DDR4. DQS to DQ and DQM, DQS to CLK, and CLK to address and control. Does such a document exist?
I see timing in the datasheet and references to write leveling in the reference manual, but nothing that puts it all together. This is a mature processor, there must be some documentation describing the timing requirements so I can put together my layout constraints.
Anything? TI, Xilinx and Synopsys have such information.