how to add more chip selects in T1040RDB_init_core.tcl file

gouravjain · ‎06-26-2016

Hi all,

Want to add more chip selects in T1040RDB_initcore.tcl file(original). so what i did, performed some free space testing on working chip select

	# LAW1 to IFC (CPLD) - 128K
	mem [CCSR_ADDR 0xc10] = 0x00000000
	mem [CCSR_ADDR 0xc14] = 0xFFDF0000
	mem [CCSR_ADDR 0xc18] = 0x81F00010

by changing just mem [CCSR_ADDR 0xc14] = 0xA0000000 and

# CSPR

mem [CCSR_ADDR [expr {0x124010 + $Altera_CS * 0x0C}]] = 0xA0000085

but its not working. pls tell me what else places i need to modify ??

regards,

Gourav

ufedor · ‎06-26-2016

You also need to add a MMU TLB for the 0xA0000000 in the "# MMU initialization" section.

gouravjain · ‎06-28-2016

hi,

modified as per your suggestion but still im getting "0x0000" from Hardware Diagnostic console...

Reading from target...

Read 0x0000 at address: 0xA0000000

Task Execution finished. Disconnecting ...

Below is the modified tcl file. pls let me know if im missing something.

# #######################################################################################

# Initialization file for T1040 RDB board

# Clock Configuration:

# CPU0: 1200/1400MHz, CCB: 600MHz,

# DDR: 800MHz (1600 MT/s data rate) (Asynchronous), IFC: 150MHz,

# FMAN1: 600MHz, QMAN: 300MHz, PME: 300MHz

# #######################################################################################

# Choose which core will initialize the board

variable master_core 0

variable ECC_EN 1

variable CCSRBAR 0xFE000000

proc CCSR_ADDR {reg_off} {

global CCSRBAR

return i:0x[format %x [expr {$CCSRBAR + $reg_off}]]

}

proc init_board {} {

# disable Boot Space Translation

mem [CCSR_ADDR 0x28] = 0x00000000

##################################################################################

# Local Access Windows Setup

# LAW0 to IFC (NOR) - 128M

mem [CCSR_ADDR 0xc00] = 0x00000000

mem [CCSR_ADDR 0xc04] = 0xE8000000

mem [CCSR_ADDR 0xc08] = 0x81F0001A

# LAW1 to IFC (Altera) - 128K

mem [CCSR_ADDR 0xc10] = 0x00000000

mem [CCSR_ADDR 0xc14] = 0xA0000000

mem [CCSR_ADDR 0xc18] = 0x81F00010

# LAW2 to DCSR - 4M

mem [CCSR_ADDR 0xc20] = 0x00000000

mem [CCSR_ADDR 0xc24] = 0xF0000000

mem [CCSR_ADDR 0xc28] = 0x81D00015

# LAW3 to IFC (NAND) - 64K

mem [CCSR_ADDR 0xc30] = 0x00000000

mem [CCSR_ADDR 0xc34] = 0xFF800000

mem [CCSR_ADDR 0xc38] = 0x81F0000F

# LAW4 to Raycom0 - 64k

mem [CCSR_ADDR 0xc40] = 0x00000000

mem [CCSR_ADDR 0xc44] = 0xa0000000

mem [CCSR_ADDR 0xc48] = 0x81F0000F

# LAW5 to Raycom1 - 64k

mem [CCSR_ADDR 0xc50] = 0x00000000

mem [CCSR_ADDR 0xc54] = 0xb0000000

mem [CCSR_ADDR 0xc58] = 0x81F0000F

# LAW6 to XRT0 - 64k

mem [CCSR_ADDR 0xc60] = 0x00000000

mem [CCSR_ADDR 0xc64] = 0xc0000000

mem [CCSR_ADDR 0xc68] = 0x81F0000F

# LAW15 to DDR (Memory Complex 1) - 2G

mem [CCSR_ADDR 0xcf0] = 0x00000000

mem [CCSR_ADDR 0xcf4] = 0x00000000

mem [CCSR_ADDR 0xcf8] = 0x8100001E

##################################################################################

# DDR Controller Setup

# Get DDR type: 0 - DDR4; 1 - DDR3

# set DCFG_CCSR_PORSR2 [mem [CCSR_ADDR 0xE0004]]

# set DDR_TYPE [expr ($DCFG_CCSR_PORSR2 & 0x20000000) >> 29]

# DDR_SDRAM_CFG

mem [CCSR_ADDR 0x8110] = 0x47040000

# DDR_CS0_BNDS

mem [CCSR_ADDR 0x8000] = 0x7F

# DDR_CS1_BNDS

mem [CCSR_ADDR 0x8008] = 0x00000000

# DDR_CS0_CONFIG

mem [CCSR_ADDR 0x8080] = 0x80044302

# DDR_CS1_CONFIG

mem [CCSR_ADDR 0x8084] = 0x00000000

# DDR_CS0_CONFIG_2

mem [CCSR_ADDR 0x80c0] = 0x00000000

# DDR_CS1_CONFIG_2

mem [CCSR_ADDR 0x80c4] = 0x00000000

# DDR_TIMING_CFG_3

mem [CCSR_ADDR 0x8100] = 0x00060000

# DDR_TIMING_CFG_0

mem [CCSR_ADDR 0x8104] = 0x4011000c

# DDR_TIMING_CFG_1

mem [CCSR_ADDR 0x8108] = 0x6e6a0644

# DDR_TIMING_CFG_2

mem [CCSR_ADDR 0x810C] = 0x002880d0

# DDR_SDRAM_CFG_2

mem [CCSR_ADDR 0x8114] = 0x00401900

# DDR_SDRAM_MODE

mem [CCSR_ADDR 0x8118] = 0x00441420

# DDR_SDRAM_MODE_2

mem [CCSR_ADDR 0x811C] = 0x00800000

# DDR_SDRAM_MODE_3

mem [CCSR_ADDR 0x8200] = 0x00001420

# DDR_SDRAM_MODE_4

mem [CCSR_ADDR 0x8204] = 0x00800000

# DDR_SDRAM_MODE_5

mem [CCSR_ADDR 0x8208] = 0x000

# DDR_SDRAM_MODE_6

mem [CCSR_ADDR 0x820C] = 0x00000000

# DDR_SDRAM_MODE_7

mem [CCSR_ADDR 0x8210] = 0x00000

# DDR_SDRAM_MODE_8

mem [CCSR_ADDR 0x8214] = 0x00000000

# DDR_SDRAM_MD_CNTL

mem [CCSR_ADDR 0x8120] = 0x00000000

# DDR_SDRAM_INTERVAL

mem [CCSR_ADDR 0x8124] = 0x06180100

# DDR_DATA_INIT

mem [CCSR_ADDR 0x8128] = 0xdeadbeef

# DDR_SDRAM_CLK_CNTL

mem [CCSR_ADDR 0x8130] = 0x02000000

# DDR_INIT_ADDR

mem [CCSR_ADDR 0x8148] = 0x00000000

# DDR_INIT_EXT_ADDRESS

mem [CCSR_ADDR 0x814C] = 0x00000000

# DDR_TIMING_CFG_4

mem [CCSR_ADDR 0x8160] = 0x00000001

# DDR_TIMING_CFG_5

mem [CCSR_ADDR 0x8164] = 0x02401400

# DDR_ZQ_CNTL

mem [CCSR_ADDR 0x8170] = 0x89080600

# DDR_WRLVL_CNTL

mem [CCSR_ADDR 0x8174] = 0xc675f606

# DDR_SR_CNTR

mem [CCSR_ADDR 0x817c] = 0x00000000

# DDR_WRLVL_CNTL_2

mem [CCSR_ADDR 0x8190] = 0x07080809

# DDR_WRLVL_CNTL_3

mem [CCSR_ADDR 0x8194] = 0x090A0A00

# DDR_DDRCDR_1

mem [CCSR_ADDR 0x8b28] = 0x80040000

# DDR_DDRCDR_2

mem [CCSR_ADDR 0x8b2c] = 0x00000001

# DDR_ERR_DISABLE - DISABLE

mem [CCSR_ADDR 0x8e44] = 0x00000000

# DDR_ERR_SBE

mem [CCSR_ADDR 0x8e58] = 0x00000000

# delay before enable

wait 500

# DDR_SDRAM_CFG

mem [CCSR_ADDR 0x8110] = 0xc7040000

# wait for DRAM data initialization

wait 1500

##################################################################################

# eSPI Setup

# SPMODE

mem [CCSR_ADDR 0x110000] = 0x80000403

# SPIM - catch all events

mem [CCSR_ADDR 0x110008] = 0x00000000

# SPMODE0

mem [CCSR_ADDR 0x110020] = 0x2E170008

##################################################################################

# IFC Controller Setup

global ECC_EN

set ECC_ENC_EN 0x[format %x [expr $ECC_EN << 31]]

set ECC_DEC_EN 0x[format %x [expr $ECC_EN << 26]]

set NOR_CS 0

set NAND_CS 1

set Altera_CS 2

set Raycom0_CS 3

set Raycom1_CS 4

set xrt0_CS 5

# Altera, addr 0xFFDF0000, 128K size, 16-bit, GPCM, Valid

# CSPR_EXT

mem [CCSR_ADDR [expr {0x12400C + $Altera_CS * 0x0C}]] = 0x00000000

# CSPR

mem [CCSR_ADDR [expr {0x124010 + $Altera_CS * 0x0C}]] = 0xA0000105

#

mem [CCSR_ADDR [expr {0x1240A0 + $Altera_CS * 0x0C}]] = 0xFFFE0000

# CSOR

mem [CCSR_ADDR [expr {0x124130 + $Altera_CS * 0x0C}]] = 0x00000000

# IFC_FTIM0

mem [CCSR_ADDR [expr {0x1241C0 + $Altera_CS * 0x30}]] = 0xE00E000E

# IFC_FTIM1

mem [CCSR_ADDR [expr {0x1241C4 + $Altera_CS * 0x30}]] = 0x0E001F00

# IFC_FTIM2

mem [CCSR_ADDR [expr {0x1241C8 + $Altera_CS * 0x30}]] = 0x0E00001F

# IFC_FTIM3

mem [CCSR_ADDR [expr {0x1241CC + $Altera_CS * 0x30}]] = 0x00000000

# NOR Flash, addr 0xE8000000, 128M size, 16-bit NOR

# CSPR_EXT

mem [CCSR_ADDR [expr {0x12400C + $NOR_CS * 0x0C}]] = 0x00000000

# CSPR

mem [CCSR_ADDR [expr {0x124010 + $NOR_CS * 0x0C}]] = 0xE8000101

# AMASK

mem [CCSR_ADDR [expr {0x1240A0 + $NOR_CS * 0x0C}]] = 0xF8000000

# CSOR

mem [CCSR_ADDR [expr {0x124130 + $NOR_CS * 0x0C}]] = 0x0000000C

# IFC_FTIM0

mem [CCSR_ADDR [expr {0x1241C0 + $NOR_CS * 0x30}]] = 0x40050005

# IFC_FTIM1

mem [CCSR_ADDR [expr {0x1241C4 + $NOR_CS * 0x30}]] = 0x35001A13

# IFC_FTIM2

mem [CCSR_ADDR [expr {0x1241C8 + $NOR_CS * 0x30}]] = 0x0410381C

# IFC_FTIM3

mem [CCSR_ADDR [expr {0x1241CC + $NOR_CS * 0x30}]] = 0x00000000

# NAND Flash, addr 0xFF800000, 64K size, 8-bit NAND

# CSPR_EXT

mem [CCSR_ADDR [expr {0x12400C + $NAND_CS * 0x0C}]] = 0x00000000

# CSPR

mem [CCSR_ADDR [expr {0x124010 + $NAND_CS * 0x0C}]] = 0xFF800083

# AMASK

mem [CCSR_ADDR [expr {0x1240A0 + $NAND_CS * 0x0C}]] = 0xFFFF0000

# CSOR

mem [CCSR_ADDR [expr {0x124130 + $NAND_CS * 0x0C}]] = 0x[format %x [expr 0x0110A100 | $ECC_ENC_EN | $ECC_DEC_EN]]

# IFC_FTIM0

mem [CCSR_ADDR [expr {0x1241C0 + $NAND_CS * 0x30}]] = 0x0E18070A

# IFC_FTIM1

mem [CCSR_ADDR [expr {0x1241C4 + $NAND_CS * 0x30}]] = 0x32390E18

# IFC_FTIM2

mem [CCSR_ADDR [expr {0x1241C8 + $NAND_CS * 0x30}]] = 0x01E0501E

# IFC_FTIM3

mem [CCSR_ADDR [expr {0x1241CC + $NAND_CS * 0x30}]] = 0x00000000

# Raycom 0, addr 0xA0000000, 64K size, 8-bit device.

# CSPR_EXT

mem [CCSR_ADDR [expr {0x12400C + $Raycom0_CS * 0x0C}]] = 0x00000000

# CSPR

mem [CCSR_ADDR [expr {0x124010 + $Raycom0_CS * 0x0C}]] = 0xA0000085

#AMASK

mem [CCSR_ADDR [expr {0x1240A0 + $Raycom0_CS * 0x0C}]] = 0xFFFF0000

# CSOR

mem [CCSR_ADDR [expr {0x124130 + $Raycom0_CS * 0x0C}]] = 0x00000000

# IFC_FTIM0

mem [CCSR_ADDR [expr {0x1241C0 + $Raycom0_CS * 0x30}]] = 0xE00E000E

# IFC_FTIM1

mem [CCSR_ADDR [expr {0x1241C4 + $Raycom0_CS * 0x30}]] = 0x0E001F00

# IFC_FTIM2

mem [CCSR_ADDR [expr {0x1241C8 + $Raycom0_CS * 0x30}]] = 0x0E00001F

# IFC_FTIM3

mem [CCSR_ADDR [expr {0x1241CC + $Raycom0_CS * 0x30}]] = 0x00000000

# Raycom 1, addr 0xB0000000, 64K size, 8-bit device.

# CSPR_EXT

mem [CCSR_ADDR [expr {0x12400C + $Raycom1_CS * 0x0C}]] = 0x00000000

# CSPR

mem [CCSR_ADDR [expr {0x124010 + $Raycom1_CS * 0x0C}]] = 0xB0000085

#

mem [CCSR_ADDR [expr {0x1240A0 + $Raycom1_CS * 0x0C}]] = 0xFFFF0000

# CSOR

mem [CCSR_ADDR [expr {0x124130 + $Raycom1_CS * 0x0C}]] = 0x00000000

# IFC_FTIM0

mem [CCSR_ADDR [expr {0x1241C0 + $Raycom1_CS * 0x30}]] = 0xE00E000E

# IFC_FTIM1

mem [CCSR_ADDR [expr {0x1241C4 + $Raycom1_CS * 0x30}]] = 0x0E001F00

# IFC_FTIM2

mem [CCSR_ADDR [expr {0x1241C8 + $Raycom1_CS * 0x30}]] = 0x0E00001F

# IFC_FTIM3

mem [CCSR_ADDR [expr {0x1241CC + $Raycom1_CS * 0x30}]] = 0x00000000

# XRT0 , addr 0xC0000000, 64K size, 8-bit device.

# CSPR_EXT

mem [CCSR_ADDR [expr {0x12400C + $xrt0_CS * 0x0C}]] = 0x00000000

# CSPR

mem [CCSR_ADDR [expr {0x124010 + $xrt0_CS * 0x0C}]] = 0xC0000085

#

mem [CCSR_ADDR [expr {0x1240A0 + $xrt0_CS * 0x0C}]] = 0xFFFF0000

# CSOR

mem [CCSR_ADDR [expr {0x124130 + $xrt0_CS * 0x0C}]] = 0x00000000

# IFC_FTIM0

mem [CCSR_ADDR [expr {0x1241C0 + $xrt0_CS * 0x30}]] = 0xE00E000E

# IFC_FTIM1

mem [CCSR_ADDR [expr {0x1241C4 + $xrt0_CS * 0x30}]] = 0x0E001F00

# IFC_FTIM2

mem [CCSR_ADDR [expr {0x1241C8 + $xrt0_CS * 0x30}]] = 0x0E00001F

# IFC_FTIM3

mem [CCSR_ADDR [expr {0x1241CC + $xrt0_CS * 0x30}]] = 0x00000000

}

proc T1040RDB_init_core {} {

global master_core

variable CAM_GROUP "regPPCTLB1/"

variable SPR_GROUP "e5500 Special Purpose Registers/"

variable GPR_GROUP "General Purpose Registers/"

##################################################################################

#

# Memory Map

#

# 0x00000000 0x7FFFFFFF DDR 2G

# 0xE8000000 0xEFFFFFFF NOR 128M

# 0xF0000000 0xF03FFFFF DCSR 4M

# 0xFE000000 0xFEFFFFFF CCSR Space 16M

# 0xFF800000 0xFF80FFFF NAND 64K

# 0xFFDF0000 0xFFE0FFFF CPLD 128K

# 0xFFFFF000 0xFFFFFFFF Boot Page 4K

#

##################################################################################

# #################################################################################

# MMU initialization

# define 16M TLB entry 1 : 0xFE000000 - 0xFEFFFFFF for CCSR_ADDR cache inhibited, guarded

reg ${CAM_GROUP}L2MMU_CAM1 = 0x7000000A1C08000000000000FE00000000000000FE000001

# define 256M TLB entry 2 : 0xE8000000 - 0xEFFFFFFF for NOR cache inhibited, guarded

reg ${CAM_GROUP}L2MMU_CAM2 = 0x9000000A1C08000000000000E000000000000000E0000001

# define 1G TLB entry 3 : 0x00000000 - 0x3FFFFFFF for DDR cache inhibited

reg ${CAM_GROUP}L2MMU_CAM3 = 0xA00000081C08000000000000000000000000000000000001

# define 1G TLB entry 4 : 0x40000000 - 0x7FFFFFFF for DDR cache inhibited

reg ${CAM_GROUP}L2MMU_CAM4 = 0xA00000081C08000000000000400000000000000040000001

# define 4MB TLB entry 5 : 0xF0000000 - 0xF03FFFFF for DCSR cache inhibited, guarded

reg ${CAM_GROUP}L2MMU_CAM5 = 0x6000000A1C08000000000000F000000000000000F0000001

# define 256K TLB entry 6 : 0xFFDF0000 - 0xFFE0FFFF for CPLD cache inhibited, guarded

reg ${CAM_GROUP}L2MMU_CAM6 = 0x4000000A1C08000000000000A000000000000000A0000001

# define 64K TLB entry 7 : 0xFF800000 - 0xFF80FFFF for NAND cache inhibited, guarded

reg ${CAM_GROUP}L2MMU_CAM7 = 0x3000000A1C08000000000000FF80000000000000FF800001

# init board, only when the init is run for master core

variable proc_id [expr {[reg ${SPR_GROUP}PIR %d -np] >> 5 }]

if {$proc_id == $master_core} {

init_board

}

##################################################################################

# Interrupt vectors initialization

# interrupt vectors in RAM at 0x[expr {${proc_id} << 1}]0000000

# IVPR (default reset value)

reg ${SPR_GROUP}IVPR = 0x[expr {${proc_id} << 1}]0000000

# interrupt vector offset registers

# IVOR0 - critical input

reg ${SPR_GROUP}IVOR0 = 0x00000100

# IVOR1 - machine check

reg ${SPR_GROUP}IVOR1 = 0x00000200

# IVOR2 - data storage

reg ${SPR_GROUP}IVOR2 = 0x00000300

# IVOR3 - instruction storage

reg ${SPR_GROUP}IVOR3 = 0x00000400

# IVOR4 - external input

reg ${SPR_GROUP}IVOR4 = 0x00000500

# IVOR5 - alignment

reg ${SPR_GROUP}IVOR5 = 0x00000600

# IVOR6 - program

reg ${SPR_GROUP}IVOR6 = 0x00000700

# IVOR7 - floating point unavailable

reg ${SPR_GROUP}IVOR7 = 0x00000800

# IVOR8 - system call

reg ${SPR_GROUP}IVOR8 = 0x00000C00

# IVOR10 - decrementer

reg ${SPR_GROUP}IVOR10 = 0x00000900

# IVOR11 - fixed-interval timer interrupt

reg ${SPR_GROUP}IVOR11 = 0x00000F00

# IVOR12 - watchdog timer interrupt

reg ${SPR_GROUP}IVOR12 = 0x00000B00

# IVOR13 - data TLB errror

reg ${SPR_GROUP}IVOR13 = 0x00001100

# IVOR14 - instruction TLB error

reg ${SPR_GROUP}IVOR14 = 0x00001000

# IVOR15 - debug

reg ${SPR_GROUP}IVOR15 = 0x00001500

# IVOR35 - performance monitor

reg ${SPR_GROUP}IVOR35 = 0x00001900

##################################################################################

# Enable branch prediction

reg ${SPR_GROUP}BUCSR = 0x01400201

##################################################################################

# Debugger settings

# enable machine check

reg ${SPR_GROUP}HID0 = 0x80000000

# enable floating point

reg ${SPR_GROUP}MSR = 0x00002000

# infinite loop at program exception to prevent taking the exception again

mem v:0x[expr {${proc_id} << 1}]0000700 = 0x48000000

# prevent stack unwinding at entry_point/reset when stack pointer is not initialized

reg ${GPR_GROUP}SP = 0x0000000F

if {$proc_id == $master_core} {

# DCFG_BRR - enable all cores

mem [CCSR_ADDR 0xe00e4] = 0x0000000F

# RCPM_CTBENR - enable all cores' timebase

mem [CCSR_ADDR 0xe2084] = 0x0000000F

}

proc envsetup {} {

# Environment Setup

radix x

config hexprefix 0x

config MemIdentifier v

config MemWidth 32

config MemAccess 32

config MemSwap off

}

#-------------------------------------------------------------------------------

# Main

#-------------------------------------------------------------------------------

envsetup

T1040RDB_init_core

ufedor · ‎06-30-2016

Sorry for the delay.

I believe that the TCL is correct.

There is one more configuration file which has to be changed - MEM - please see attached.

gouravjain · ‎07-12-2016

Hi,

Now .tcl is working with your suggestion. After that i tried to make changes in u-boot also, but its got hanged.

Here are the changes made by me,

1) T104xRDB.h

#define CONFIG_SYS_RAYCOM1_BASE 0xFF900000

#define CONFIG_SYS_RAYCOM1_BASE_PHYS (0xf00000000ull | CONFIG_SYS_RAYCOM1_BASE)

#define CONFIG_SYS_CSPR3_EXT (0xf)

#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_RAYCOM1_BASE_PHYS) \

| CSPR_PORT_SIZE_8 \

| CSPR_MSEL_GPCM \

| CSPR_V)

#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)

#define CONFIG_SYS_CSOR3 0x0

/* RAYCOM1 Timing parameters for IFC CS2 */

#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \

FTIM0_GPCM_TEADC(0x0e) | \

FTIM0_GPCM_TEAHC(0x0e))

#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \

FTIM1_GPCM_TRAD(0x1f))

#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \

FTIM2_GPCM_TCH(0x0) | \

FTIM2_GPCM_TWP(0x1f))

#define CONFIG_SYS_CS3_FTIM3 0x0

2) tlb.c

#ifdef CONFIG_SYS_RAYCOM1_BASE

SET_TLB_ENTRY(1, CONFIG_SYS_RAYCOM1_BASE, CONFIG_SYS_RAYCOM1_BASE_PHYS,

MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

0, 14, BOOKE_PAGESZ_256K, 1),

#endif

3) law.c

#ifdef CONFIG_SYS_RAYCOM1_BASE_PHYS

SET_LAW(CONFIG_SYS_RAYCOM1_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),

#endif

pls let me know where im doing wrong.

--

Gourav jain

ufedor · ‎07-12-2016

Please create new question concerning the U-Boot.

how to add more chip selects in T1040RDB_init_core.tcl file

how to add more chip selects in T1040RDB_init_core.tcl file

QorIQ T1 Devices