Hello,
We made a board with reference of T4240RDB, recently we met a problem which is shown in the title. After many checks,
we found an abnormal phenomenon:
The impedance in question is not characterized, so it is not specified what is its normal value.
Hi,I need your help.Thanks a lot.
Please confirm whether the processor is capable to complete its POR sequence - refer to the T4240 RM, 4.6.1 Power-on reset sequence.
Thank you for your reply. But Why the impedance between VDD_OVDD_P1V8 and GND is so low?
Please provide the processor connection schematics as PDF.
Hi,thank you for your reply.
I am a fresher here. How Can I upload the PDF file ?
Just attach it to response.
Now please describe the processor behaviour and restate the question.
And the second abnormal state is :
The 1st foot of JTAG connector is short circuit.
and the net of the 1st foot, named "COP_TDO" is directly connected to T4240's pin,which is K42.
Now, we are so worried that there is something wrong with the inside of the T4240.
OK,Let me state the problem from the beginning.
Actually, last week, my board had just been ready for the frist time programme. But the first time we connected the debug device to the board, the problem happened. The figure is shown below.
OK, the Chinese characters could be ignored. So, we began to check the relevant hardware.
Finally,we found two abnormal states.