T1042 Serdes

[gokulkrishnan]

Hi, 

I am using the T1042 in one of my designs. I intend on using the first 3 serdes SD1[0-2] for 1G serdes and the remianing 4 SD1[3:7] as Pcie gen2. I would like to know if this configuration is possible. Next is what are the clock requirements for the same? Also can you guide me with what configuration changes need to be made to accommodate this particular configuration. 

Regards 

Gokul

[r8070z]

Have a great day,

If you mean 3 SGMII x1 ports and  PCIE x4 port, then this configuration is not possible. You can check for available serdes configurations in section 31.1.1.2.2 SerDes Protocols of the QorIQ T1040 Reference Manual (REV 1). The manual can be downloaded from the nxp site. I also attached serdes configurations color table from the manual where for the T1042 SGMII ports are sg.m1…sg.m5.

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[gokulkrishnan]

Hi Serguei,

I'm sorry for not being clear. What i meant is PCIE Gen2 2 ports and 3 1G Serdes ports. I'm hoping this would be possible looking at the above table.

Ie Configuration 81, 86, 87.

Regards 

Gokul