How to configure T2080 to 10GBase-KR?

[manjunath_ganga]

We are using T2080 and configuring board for 10GBase-KR. By default Serdes setting of XFI is done, Lane reset and reconfiguration is performed as per section 19.6.4.1. We enabled link training and auto negotiation, but link is down. Is there any definite order link training and auto negotiation to performed with other setting?

External PHY is configured correctly.

[manjunath_ganga]

We started using XFI with default setting. After completing basic functionality test, we moved to 10GBase-KR and anticipating only changes related to Lane reset and reconfiguration. 

[yipingwang]

Hello MANJUNATH GANGADHARA,

We have T2080QDS supports XFI through Lane A/B/C/D on Serdes 1 routed to a on-board SFP+ cages, which to house optical module (fiber cable) or direct attach cable(copper), the copper cable is used to emulate 10GBASE-KR scenario.

The attached is 10GBASE-KR Linux Kernel driver in drivers/net/phy/fsl_10gkr.c, you could refer to the whole procedure in the probe function.

You could modify and build Linux Kernel image to support 10GBASE-KR and running on your custom board, please modify dts as the following and configure CONFIG_FSL_10GBASE_KR in .config.

                  fm1mac9: ethernet@f0000 { /* DTSEC9/10GEC1 */
                        phy-handle = <&xfiphy9>;
                        phy-connection-type = "xgmii";
                    };

                           xfimdio9: mdio@fd000 {
                                status = "ok";
                                xfiphy9: ethernet-phy@3 {
                                        compatible = "ethernet-phy-ieee802.3-c45";
                                        lane-instance = "serdes-1,lane-a";
                                        reg = <0x3>;
                                };

Thanks,

Yiping

[manjunath_ganga]

Hello Wang,

Thanks for sharing probe function.

After changes i always see TRAIN_FAIL (Training Failure has been detected) and LNK_STAT is always down. Is there any order in doing link training and auto-negotiation? Is there any other parameters to adjust before enabling the link training.

Link training on external PHY is enabled and status looks fine. 

Regards,

Manjunath

[yipingwang]

Hello Manjunath,

Please refer to the link training procedure addressed in xgkr_wq_state_machine, please refer to the section after  "dev_info(&phydev->dev, "is training.\n")".

Please enable training through XFI 10GBASE-KR PMD Control Register, and check MDIO_XFI_10GKR_PMD_SR, if TRAIN_FAIL, please reset lane then start training again until LT training succeed(or PMD_STATUS_SUP_STAT and PMD_STATUS_FRAME_LOCK) before the dead line.

Have a great day,
TIC

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[manjunath_ganga]

Hello Yiping,

I didn't see any time PMD_STATUS_FRAME_LOCK  bit getting SET, another bit PMD_STATUS_SUP_STAT  is set throughout the link training attempt. My understanding is  PMD_STATUS_FRAME_LOCK  indicates link training has started. How to understand why PMD_STATUS_FRAME_LOCK  bit is not SET.

Regards,

Manjunath

[yipingwang]

Hello Manjunath,

When training failure occurs, the link is kept in an inoperable state (PCS is not allowed to lock). 

PMD_STATUS_FRAME_LOCK is not set, the training frame delineation is not detected.

Please refer to the following driver code for link training, if TRAIN_FAIL is set, please reset lane and start LT again, wait for a while to check FSL_XFI_KR_PMD_STATUS again. If TRAIN_FAIL is not detected, please check whether PMD_STATUS_SUP_STAT and PMD_STATUS_FRAME_LOCK are set as well.

                dead_line = jiffies + msecs_to_jiffies(500);
                while (time_before(jiffies, dead_line)) {
                        val = phy_read_mmd(phydev, FSL_XFI_PMD,
                                        FSL_XFI_KR_PMD_STATUS);
                        if (val & TRAIN_FAIL) {
                                /* LT failed already, reset lane to avoid
                                 * it run into hanging, then start LT again.
                                 */
                                reset_gcr0(inst);
                                start_lt(phydev);
                        } else if (val & PMD_STATUS_SUP_STAT &&
                                        val & PMD_STATUS_FRAME_LOCK)
                                break;
                        usleep_range(100, 500);
                }

If your problem remains, would you please provide your driver code used for link training part.

Have a great day,
TIC

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[manjunath_ganga]

Hello Yiping,

We found training is success and link is UP. But link state is changing to DOWN within 500ms. Can you tell what is condition or reasons for processor to change the state to DOWN? Is there any post link training procedure to be performed?

Some of the register value after training success:

MDIO_XFI_10GKR_PMD_SR(0x97) = 0x0001

MDIO_XFI_10GKR_LP_SRR(0x99) = 0x8000

MDIO_XFI_10GKR_LD_SRR(0x9B) = 0x8000

MDIO_XF_AN_SR(0x1) = 0x0049

Do you need any other information?

Regards,

Manjunath

[yipingwang]

Hello Manjunath,

Please refer to the following section in xgkr_wq_state_machine in fsl_10gkr.c, after training succeeds, please disable training through writing XFI 10GBASE-KR PMD Control Register.

                /* check LT result */
                if (is_link_training_fail(phydev)) {
                        /* reset state machine */
                        init_inst(inst, 0);
                        continue;
                } else {
                        stop_lt(phydev);
                        s_m->running = false;
                        s_m->link_up = true;
                        dev_info(&phydev->dev, "LT training is SUCCEEDED!\n");
                        break;
                }

static void stop_lt(struct phy_device *phydev)
{
        phy_write_mmd(phydev, FSL_XFI_PMD, FSL_XFI_KR_PMD_CTRL, TRAIN_DISABLE);
}

Have a great day,
TIC

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[manjunath_ganga]

Hello Yiping,

Implementation is same as suggested by you, but link goes down within 500ms. What is the reasons for T2080 to reset the link.

Regards,

Manjunath

[manjunath_ganga]

Hello Yiping,

Do you have suggestions for me?

Regards,

Manjunath

[yipingwang]

Hello Manjunath,

The LT should be finished in 500ms, in your driver you need to set the deed_line as 500ms for the while loop, if the LT succeeds, please break the while loop immediately and disable training through writing XFI 10GBASE-KR PMD Control Register.

Have a great day,
TIC

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[manjunath_ganga]

Hello Yiping,

I saw rx_ok  with RX_READY many times and didn't see tx_ok through out link-training. Attached driver code for link training part.

Regards,

Manjunath