Problem with Freefall Detection

[joãopaulo]

I am not able to use the FXOS8700CQ accelerometer present on the kv31f board.
I would like to use the freefall function and for this I configured the following registers.

Freefall Configuration			Z < 0,3g using MFF Function 4g, 100 Hz ODR, Normal Mode
Register Name	Register Addr	Data (R/W)	Description
CTRL_REG1	0x2A	0x00 W	Standby mode for writable operations
WHO_AM_I	0x0D	Read	Check device communication (0xC7)
XYZ_DATA_CFG	0x0E	0x01 W	Hight-pass filter disabled, +/-0.488mg/LSB
CTRL_REG1	0x2A	0x18 W	Set the device in 100 Hz ODR, Standby
A_FFMT_CFG	0x15	0xA0 W	Latch enable, Freefall, Z axis
A_FFMT_THS	0x17	0x05 W	0,3g threshold
A_FFMT_COUNT	0x18	0x0A W	Debounce 100ms
CTRL_REG4	0x2D	0x04 W	FF interrupt enable
CTRL_REG5	0x2E	0x04 W	interrupt routed to INT1 pin
CTRL_REG1	0x2A	0x19 W	Set the device in 100 Hz ODR, Active Mode

- The communication is working properly because I can read the WHO_AM_I register,

- I've already followed the AN4070 document,

But it's not working, the Freefall interrupt isn't happening,

I've tried to use the 3 axes and then only one but none worked.

Is there any other register that I need to configure?

What else should I do?

Thanks 

[TomasVaverka]

Hi Joao,

You should also configure both the ipol and pp_od bits of the CTRL_REG3 register. Also make sure the corresponding GPIO pin on your MCU is configured as interrupt input with proper polarity.

Then I would recommend using a logic analyzer or an oscilloscope to know what is going on the bus and INT pin. If you are able to detect only first interrupt, then please double check if you read properly the A_FFMT_SRC register to clear the src_ffmt flag and consequently deassert the INT pin. It is also necessary to acknowledge an IRQ in your ISR usually by writing a logic 1 to a specific bit of your MCU. Without doing it, the interrupt flag on your MCU will remain active and then you will not be able to receive any further interrupts from the FXOS8700CQ.

I hope it helps.

Best regards,

Tomas