S32K3x Questions about the use of I-TCM and D-TCM

[Chris-Sun]

1. According to the S32K312 Block Diagram in the manual, there is 1 32KB I-TCM and 2 32KB D-TCMs. However, according to the attached memory map, there is 1 32KB I-TCM and 1 64KB D-TCM. This seems to be inconsistent.

2. Regarding the use of D-TCM and I-TCM, please confirm if my understanding is correct:

Is the following diagram depicting the rules for using multiple cores or multiple I-TCMs and D-TCMs?

For example, if CM7_0 wants to access CM7_1's ITCM, it can only be done through the Backdoor method. However, to access its own ITCM, both Direct and Backdoor methods can be used, is that right?

For S32K314, which only has 1 core, if I want to use ITCM1, can I only use the Backdoor method?

I understand that ITCM1 should also be a resource of this core. Is the difference between Direct and Backdoor methods only in the configuration of the ld file's MEMORY, based on the memory map addresses?

So, for S32K312, which also only has 1 core, what is the difference between using ITCM/DTCM with Direct or Backdoor methods?

3. Regarding this diagram, my understanding is that it shows the actions to be taken when using TCM use TCMs of the disabled core on multi-core devices . 

Why is the enabled core configured in Wait mode? Does this mean that the operation of the enabled core will be abnormal?

For the previously mentioned S32K314 with only 1 core, is it still necessary to perform these steps when using ITCM1?

Additionally, according to the description in the manual, the chip does not support Wait mode...

If my understanding is incorrect, please kindly point it out.

I am just starting to learn how to use TCM.

Thanks a lot !

[petervlna]

Hello,

1. According to the S32K312 Block Diagram in the manual, there is 1 32KB I-TCM and 2 32KB D-TCMs. However, according to the attached memory map, there is 1 32KB I-TCM and 1 64KB D-TCM. This seems to be inconsistent.

I excel there is just size summary of DTCM0 (assigned to core0). Physically there are 2 D-TCM modules.

2. Regarding the use of D-TCM and I-TCM, please confirm if my understanding is correct:
Is the following diagram depicting the rules for using multiple cores or multiple I-TCMs and D-TCMs?

If you use it as system RAM. i.e. you are accessing by different master than the core this TCM is related to, you will have to use backdoor access address range.

For S32K314, which only has 1 core, if I want to use ITCM1, can I only use the Backdoor method?

Yes

I understand that ITCM1 should also be a resource of this core. Is the difference between Direct and Backdoor methods only in the configuration of the ld file's MEMORY, based on the memory map addresses?

It differs based on the accessing master.

So, for S32K312, which also only has 1 core, what is the difference between using ITCM/DTCM with Direct or Backdoor methods?

Answered above.

3. Regarding this diagram, my understanding is that it shows the actions to be taken when using TCM use TCMs of the disabled core on multi-core devices .

Why is the enabled core configured in Wait mode? Does this mean that the operation of the enabled core will be abnormal?

Not sure about the context here, but if the core is in wait state then it is not executing any instruction and waiting for wake up. Usually used in idle loops.

For the previously mentioned S32K314 with only 1 core, is it still necessary to perform these steps when using ITCM1?
Additionally, according to the description in the manual, the chip does not support Wait mode...

Again, it depends on the accessing master.

Best regards,

Peter

[Chris-Sun]

Hi @petervlna 

Thank you for your response to my post.

Your response has been helpful to me.

There may have been some errors in my previous description, so I have additional questions:

1. Taking S32K314 as an example, it only has 1 core, 1 I-TCM, and 1 D-TCM. However, in the memory map, there are 2 I-TCM Background and 2 D-TCM Background. Can you please explain why?

2. Taking S32K312 as an example, it only has 1 core. Is it sufficient to access I-TCM and D-TCM using the Direct method? Why is there a need for Background?

3. In the memory map, the numbers("0","1") assigned to ITCM0, ITCM1, DTCM0, DTCM1, etc., do they correspond to the cores of the chip or the masters?

Best regards,
Chris

[petervlna]

Hello,

1. Taking S32K314 as an example, it only has 1 core, 1 I-TCM, and 1 D-TCM. However, in the memory map, there are 2 I-TCM Background and 2 D-TCM Background. Can you please explain why?

The excel sheet is incorrect. there is not available second backdoor instance.

2. Taking S32K312 as an example, it only has 1 core. Is it sufficient to access I-TCM and D-TCM using the Direct method? Why is there a need for Background?

If you need access to TCM from other masters. Like DMA.

3. In the memory map, the numbers("0","1") assigned to ITCM0, ITCM1, DTCM0, DTCM1, etc., do they correspond to the cores of the chip or the masters?

to the cores.

Best regards,

Peter

[Chris-Sun]

Hi @petervlna 

Thank you for your response to my post.

Your response has been helpful to me.

There is another question:

Section 3.4 of the manual describes  "In order to allow use of ITCM
and DTCM of the disabled core as system memories the following steps must be executed by enabled core："

In step2,“This configures the core operation in Wait mode. ”

But in section 41.10.1 it mentions "This chip does not support Stop and Wait modes. The only low-power mode it supports is Standby. " 

The description here regarding the "wait state" is contradictory.

For S32K3XXX, should these steps mentioned in section 3.4 be executed?

[petervlna]

Hello,

It refer to wait mode which refer as core is disabled.

Usually when you have dummy idle loop you put core in no execution state by instructions halt or wait.

Typically in OS you have idle task. And you don't want to put there while(1) or for(;;) as the core will be executing in loop such instruction which will consume the power.

Instead you will use halt/wait which will stop core execution in iddle loop and lower power consumption.

The situation you posted is exactly for such cores in wait/halt state.

It has nothing to do with mode entry module and device power modes.

Best regards,

Peter

[Chris-Sun]

Hi @petervlna 

Thank you for your response to my post.

Your response resolved my confusion.

According to Section 3.4 of the manual:

"using DTCM of the disabled core as system memories, the following steps must be executed by the enabled core:

1. Write 1 to MC_ME's PRTN2_COFB1_CLKEN[REQ62] field for Cortex-M7_0, PRTN2_COFB1_CLKEN[REQ63] field for Cortex-M7_1, PRTN2_COFB2_CLKEN[REQ64] field for Cortex-M7_2, and PRTN2_COFB2_CLKEN[REQ65] field for Cortex-M7_3. This enables the Cortex-M7 core's TCM controller clock.

2 . Write 1 to DCM_GPR's DCMRWF4[CM7_0_CPUWAIT] field for Cortex-M7_0, DCMRWF4[CM7_1_CPUWAIT] field for Cortex-M7_1, DCMRWF4[CM7_2_CPUWAIT] field for Cortex-M7_2, and DCMRWF4[CM7_3_CPUWAIT] field for Cortex-M7_3. This configures the core operation in Wait mode.

3. Write 1 to MC_ME's PRTN0_CORE0_PCONF[CCE] field for Cortex-M7_0, PRTN0_CORE1_PCONF[CCE] field for Cortex-M7 _1, PRTN0_CORE4_PCONF[CCE] field for Cortex-M7_2, and PRTN0_CORE3_PCONF[CCE] field for Cortex-M7_3. This enables the Cortex-M7 core's clock.

"

1. On a multi-core device, are these operations performed by the enabled core to configure its own registers?

2. If it is a single-core device (such as only core0), do I need to configure MC_ME's PRTN2_COFB1_CLKEN[REQ62] and MC_ME's PRTN0_CORE0_PCONF[CCE] before using TCM? In my S32K312 project, I couldn't find the corresponding configuration options in S32DS.

Best regards,
Chris

[petervlna · Accepted solution]

Hello,

1. On a multi-core device, are these operations performed by the enabled core to configure its own registers?

Yes, the core which is active must configure it. You need TCMs of disabled clock to be clocked before you use them. Therefore Master which has access to these registers must configure it first. (enabled core in this case)

2. If it is a single-core device (such as only core0), do I need to configure MC_ME's PRTN2_COFB1_CLKEN[REQ62] and MC_ME's

Yes, if the TCMs are not clocked you need to enable clock for them by other active master, for example DMA.

Best regards,

Peter

[Chris-Sun]

Hi @petervlna 

Thank you for your response to my post.

I encountered an issue while configuring the TCM clock:

According to the source code of RTD, it is necessary to configure a macro definition, CLOCK_IP_HAS_TCM_CM7_0_CLK,  before configuring the TCM clock.

However, there is currently no corresponding place for CLOCK_IP_HAS_TCM_CM7_0_CLK.

I also couldn't find any configuration options for the TCM clock in S32DS software.

Should I manually modify Clock_Ip_Cfg_Defines.h to add this configuration? 

(I'm using S32K312 Project)

Best regards,
Chris

[petervlna]

Hello,

Hard to say.

I am not familiar with the RTDs here.

Since configuration of RTD for TCM is way out of original questions and require someone with experience with drivers you are using, I suggest to create a new thread for SW team.

I never tried to configure RTDs for this case, nor tested it.

you can possibly have a look here:

https://community.nxp.com/t5/S32K/DTCM-ITCM-example/m-p/1606827#M21008

Best regards,

Peter

[Chris-Sun]

Hi @petervlna 

Thank you for your response to my post.

Your response resolved my confusion.

I will create a new topic to discuss the configuration and usage of S32DS and RTD.

Best regards,
Chris