S32K396_confusion about the descripition of BCTU interrupt

[Zhougw]

When I am reading the datasheet about BCTU, I am very confused about the descripition of BCTU interrupt .

my application:

BCTU trigger 4 ADC sample, ADC0_ch1,ADC1_ch1,ADC2_ch1,ADC2_ch2.

conversion of ADC0_ch1,ADC1_ch1,ADC2_ch1 started simultaneous,then ADC2_ch2 start conversion.

And I don't use DMA to transfer ADC data.

the following come from attachment of the datasheet(.xlsx).

the following come from the datasheet.

If I configure "Event" as "CL Last"(MCR[LIST_IEN]=1), sampleing of the ADC2_ch2 just started, not finished?

I just want to find a interrupt that interrupt request when all sample of CL list finished.

[PetrS]

Hi,

this description indicates, the interrupt is triggered when ADC command is issued, not ADC conversion completed. However MCR[LIST_IEN] and MSR[LISTn_Last] description shows little bit different meaning. 
Let me check that with Apps/design team.

Anyway is your case it would be better to put results into FIFO and generate interrupt on FIFO watermark. Set FIFO watermark=3 and interrupt will be called once 4 results will be placed there, means all conversions from a list.

BR, Petr 

[Zhougw]

Maybe FIFO have its limit.

if I set FIFO watermark=2,I sample 3current and 7 other signal.

FIFO interrupt would happen 3 times? one interrupt for 3 signal, 3 interrupt for 9 signal.

[PetrS]

Hi,

yes, it can work this way. 
If you read 3 results from FIFO within interrupt, then this interrupt will be called 2 times within PWM period if 8 results are stored. In 2nd interrupt call you can read rest of result as should be finished already. FIFOCNTR indicates active entries in FIFO.

BR, Petr

[Zhougw]

when this CPU is designed for motor control, How do you plan to handle fast ADC(interrupt task) and slow adc(1ms/2ms task). what is the suggested solution
now I think maybe I should use DMA to trigger interrupt. Since it can specify ADC group and ADC channel.

[PetrS · Accepted solution]

Hi,

ideally it would be to use different ADC in normal mode for slow tasks, I think.

BR, Petr

[Zhougw]

This is important for our hardware design of controlboard, So I need to double check the usage.

PWM enable Half-period load and full period load. PWM period is 100us, so the interrupt is 50us.
PWM trigger -> TRGMUX -> BCTU0 -> ADC -> BCTU0_FIFO_FOC interrupt.
CL list configured in BCTU0:
ADC0_1 for currentU
ADC1_1 for currentV
ADC2_1 for currentW
ADC0_2 for Udc
ADC1_2 for U_KL15
ADC2_2 for U_KL30
ADC0_3 for U_Tmotor1(NTC)
ADC1_3 for U_Tmotor2(NTC)
Use FIFO in BCTU, set watermark=2.

timeline:
T0: PWM trigger generated, and trigger transfer to BCTU by TRGMUX.
T1(4~5 BCTU clock after T0): BCTU trigger ADC sample.
T2(about 1us after T1,conversion time is about 1us): currentUVW sample finished; Udc sample not finished; FOC calculation started.
T3(about 30-40us(FOC calculation time) after T2): FOC calculation finished; read ADC result of Udc,KL15,KL30,Tmotor1,Tmotor2.

In this way, I don't need to waste time waiting for other ADC(Udc,KL15,KL30,Tmotor1,Tmotor2) conversion in interrupt task, and I still get what I want.
Can that work?