S32K144 UART Ratio

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S32K144 UART Ratio

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kwakd_y
Contributor III

Hi

I am using the UART using the example code from COOK BOOK below.

I would like to change the UART speed from 9600 to 115200, but I do not know how to modify it in the code below.

Let me know how to use the modified code and USRT easily.

/*******************************************************************************************************/

void LPUART1_init(void)  /* Init. summary: 9600 baud, 1 stop bit, 8 bit format, no parity */
{
  PCC->PCCn[PCC_LPUART1_INDEX] &= ~PCC_PCCn_CGC_MASK;    /* Ensure clk disabled for config */
  PCC->PCCn[PCC_LPUART1_INDEX] |= PCC_PCCn_PCS(0b001)    /* Clock Src= 1 (SOSCDIV2_CLK) */
                               |  PCC_PCCn_CGC_MASK;     /* Enable clock for LPUART1 regs */

  LPUART1->BAUD = 0x0F000034;  /* Initialize for 9600 baud, 1 stop: */
                               /* SBR=52 (0x34): baud divisor = 8M/9600/16 = ~52 */
                               /* OSR=15: Over sampling ratio = 15+1=16 */
                               /* SBNS=0: One stop bit */
                               /* BOTHEDGE=0: receiver samples only on rising edge */
                               /* M10=0: Rx and Tx use 7 to 9 bit data characters */
                               /* RESYNCDIS=0: Resync during rec'd data word supported */
                               /* LBKDIE, RXEDGIE=0: interrupts disable */
                               /* TDMAE, RDMAE, TDMAE=0: DMA requests disabled */
                               /* MAEN1, MAEN2,  MATCFG=0: Match disabled */

  LPUART1->CTRL=0x000C0000;    /* Enable transmitter & receiver, no parity, 8 bit char: */
                               /* RE=1: Receiver enabled */
                               /* TE=1: Transmitter enabled */
                               /* PE,PT=0: No hw parity generation or checking */
                               /* M7,M,R8T9,R9T8=0: 8-bit data characters*/
                               /* DOZEEN=0: LPUART enabled in Doze mode */
                               /* ORIE,NEIE,FEIE,PEIE,TIE,TCIE,RIE,ILIE,MA1IE,MA2IE=0: no IRQ*/
                               /* TxDIR=0: TxD pin is input if in single-wire mode */
                               /* TXINV=0: TRansmit data not inverted */
                               /* RWU,WAKE=0: normal operation; rcvr not in statndby */
                               /* IDLCFG=0: one idle character */
                               /* ILT=0: Idle char bit count starts after start bit */
                               /* SBK=0: Normal transmitter operation - no break char */
                               /* LOOPS,RSRC=0: no loop back */
}

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1 Solution
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dianabatrlova
NXP TechSupport
NXP TechSupport

Hi KWAK D.Y,

I changed the code, for example, for LPUART source clock 40MHz. I assume, your oscillator and clocks settings are the same as in the LPUART example and SPLLDIV2_CLK is set to 40MHz.  

Our aim is to find such a ratio to make the error as close as possible to 0. In this case is the error -0.22%

PCC->PCCn[PCC_LPUART1_INDEX] &= ~PCC_PCCn_CGC_MASK; // Ensure clk disabled for config
PCC->PCCn[PCC_LPUART1_INDEX] |= PCC_PCCn_PCS(0b110) // Source clock for LPUART1 is SPLLDIV2_CLK 
| PCC_PCCn_CGC_MASK; // Enable clock for LPUART1 regs

LPUART1->BAUD = 0x1C00000C;  /* Initialize for 115200 baud, 1 stop: */
                               /* SBR=12 (0xC):

                                   baud divisor = Source clock/ Baud rate/ OSR+1 = 40000000/115200/29 =11.97 =>  ~12*/

                               /* OSR=28: Over sampling ratio = 28+1=29 */
                               /* SBNS=0: One stop bit */
                               /* BOTHEDGE=0: receiver samples on the rising edge*/
                               /* M10=0: Rx and Tx use 7 to 9 bit data characters */
                               /* RESYNCDIS=0: Resync during rec'd data word supported */
                               /* LBKDIE, RXEDGIE=0: interrupts disable */
                               /* TDMAE, RDMAE, TDMAE=0: DMA requests disabled */
                               /* MAEN1, MAEN2,  MATCFG=0: Match disabled */

For better understanding I recommend you to see chapter 51.4.1 Baud rate generation in the reference manual.

I hope it helps you.

Best regards,

Diana

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1,997 Views
dianabatrlova
NXP TechSupport
NXP TechSupport

Hi KWAK D.Y,

I changed the code, for example, for LPUART source clock 40MHz. I assume, your oscillator and clocks settings are the same as in the LPUART example and SPLLDIV2_CLK is set to 40MHz.  

Our aim is to find such a ratio to make the error as close as possible to 0. In this case is the error -0.22%

PCC->PCCn[PCC_LPUART1_INDEX] &= ~PCC_PCCn_CGC_MASK; // Ensure clk disabled for config
PCC->PCCn[PCC_LPUART1_INDEX] |= PCC_PCCn_PCS(0b110) // Source clock for LPUART1 is SPLLDIV2_CLK 
| PCC_PCCn_CGC_MASK; // Enable clock for LPUART1 regs

LPUART1->BAUD = 0x1C00000C;  /* Initialize for 115200 baud, 1 stop: */
                               /* SBR=12 (0xC):

                                   baud divisor = Source clock/ Baud rate/ OSR+1 = 40000000/115200/29 =11.97 =>  ~12*/

                               /* OSR=28: Over sampling ratio = 28+1=29 */
                               /* SBNS=0: One stop bit */
                               /* BOTHEDGE=0: receiver samples on the rising edge*/
                               /* M10=0: Rx and Tx use 7 to 9 bit data characters */
                               /* RESYNCDIS=0: Resync during rec'd data word supported */
                               /* LBKDIE, RXEDGIE=0: interrupts disable */
                               /* TDMAE, RDMAE, TDMAE=0: DMA requests disabled */
                               /* MAEN1, MAEN2,  MATCFG=0: Match disabled */

For better understanding I recommend you to see chapter 51.4.1 Baud rate generation in the reference manual.

I hope it helps you.

Best regards,

Diana