S32K144 BusFault while checking CCIF after launching Partition FlexNVM

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S32K144 BusFault while checking CCIF after launching Partition FlexNVM

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jh2
Contributor III

Hi,

I was hoping someone could help me shed light on an issue I'm having.

 

The problematic code

 

uint32_t eeIsFlexNvmPartitioned(void)
{
  /*
    "DEPART field contains 0xF for non-partitioned devices."
  */
  return ((SIM->FCFG1 & SIM_FCFG1_DEPART_MASK) != SIM_FCFG1_DEPART_MASK);
}

void eePartitionFlexNvm(void)
{
  while ((FTFC->FSTAT & FTFC_FSTAT_CCIF_MASK) != FTFC_FSTAT_CCIF_MASK)
  {
    /* Wait for command execution to finish. */
  }

  /*
    See S32K-RM 36.5.9.1.3 Command execution and error reporting.
  */
  if (FTFC->FSTAT & (FTFC_FSTAT_ACCERR_MASK | FTFC_FSTAT_FPVIOL_MASK))
  {
    FTFC->FSTAT |= FTFC_FSTAT_ACCERR_MASK | FTFC_FSTAT_FPVIOL_MASK;
  }

  /*
    See AN11983 and S32K-RM 36.4.4.1.6.1
  */
  FTFC->FCCOB[3] = 0x80; /* FCCOB0: Selects the PGMPART command */
  FTFC->FCCOB[2] = 0x00; /* FCCOB1: No CSEc operation */
  FTFC->FCCOB[1] = 0x00; /* FCCOB2: No CSEc operation */
  FTFC->FCCOB[0] = 0x00; /* FCCOB3: FlexRAM loaded with valid EEPROM during reset sequence */
  FTFC->FCCOB[7] = 0x02; /* FCCOB4: EEPROM data set size code: EEESIZE = 2 (4 kB) */
  FTFC->FCCOB[6] = 0x03; /* FCCOB5: FlexNVM Partition code: DEPART = 3 (Data flash: 32 kB, EEPROM backup: 32 kB) */

  /*
    Execute command.
  */
  FTFC->FSTAT |= FTFC_FSTAT_CCIF_MASK;

  /*
    This line causes a busfault.
  */
  while ((FTFC->FSTAT & FTFC_FSTAT_CCIF_MASK) != FTFC_FSTAT_CCIF_MASK)
  {
    /* Wait for command execution to finish. */
  }
}

 

Application code only calls eePartitionFlexNvm when eeIsFlexNvmPartitioned returns 0. The code is run from bank 0 P-flash. I am operating under the assumption that programming/partitioning bank 1 from bank 0 is OK.

 

The problem

When the application is run, the last line of code in eePartitionFlexNvm  causes the following fault:

 

BusFault: A bus fault has occurred during instruction prefetching. 

 

This also seems to occur when not debugging. For some reason, debugging and using step-by-step debugging seems to work well.

 

Other remarks

  • I have tried setting OCM1 in OCMDR0 and OCMDR1 to 0x3 before the command execution to no avail.
  • Executing the code from RAM seems to solve the issue, but I was under the impression this would not be necessary, and feels like a work-around rather than a proper fix.

Questions

  1. What is the mechanism behind this fault? I thought programming FlexNVM/D-flash from P-flash should not be a problem.
  2. I saw a similar problem on StackOverflow where the OT suggested "Disabling caching by writing LMEM->PCCRMR = 0;" solved their problem. Is this a valid solution? I haven't specifically enabled caching. I also do not see anything mentioned about this in AN11983 or the sample project flash_partitioning_s32k144.
  3. How can I solve this problem?

 

Kind regards,

Joey

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1 Solution
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danielmartynek
NXP TechSupport
NXP TechSupport

Hi Joey,

The command must be launched from SRAM or through JTAG/SWD.

danielmartynek_0-1607936232063.png

A function can be placed in SRAM as it is shown here:

https://community.nxp.com/t5/S32K/Linker-file-configuration-to-allow-code-execution-from-RAM/m-p/803...

 

Regards,

Daniel

 

View solution in original post

3 Replies
224 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hi Joey,

The command must be launched from SRAM or through JTAG/SWD.

danielmartynek_0-1607936232063.png

A function can be placed in SRAM as it is shown here:

https://community.nxp.com/t5/S32K/Linker-file-configuration-to-allow-code-execution-from-RAM/m-p/803...

 

Regards,

Daniel

 

View solution in original post

61 Views
PradeepAithal
Contributor II

Hi Daniel,

 

i tried this solution but still problem exist.

Do i need to enable the IRQ also?

without this change(as suggested by your previous comment) at least in debug mode if i do step operation ,i could run the SW after words.

Now with this change control is not coming out or going into of this function even after step operations.

Attached screenshot,

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jh2
Contributor III

Hi Daniel,

 

Thank you once again. I've obviously missed this part of the documentation, sorry for that.

 

Kind regards,

Joey

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