Hi Saitej,
Sorry for my delay!
Have you tried to use S32SDK S32K1xx RTM 4.0.1? It did not use Processor Expert.
In addition, there is an bare metal example of SPI in S32K1xx development package. You need to install S32K1xx development package in S32 Design Studio for ARM Version 2.2.
Best Regards,
Robin
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Hello @Robin_Shen
Thanks for the replay , sorry for confusing with my wordings in previous post , actually here am already using PAL driver & they are serving my purpose, now am in situation where i need to reuse same drivers before RTOS get started right after PIN_DRV_INIT().
here below is my code snippet
static uint8_t TxData_au8[2U] = { 0x01, 0x02 };
static uint8_t RxData_au8[2u];
static boolean SPI_Transfer_CompFlag;
static void SBC_Test(void)
{
SPI_MasterInit(&SPI_PERIInstance, &SPI_PERI_MasterConfig);
INT_SYS_SetPriority(g_lpspiIrqId[SPI_PERIInstance.instIdx], 0);
if(STATUS_SUCCESS == SPI_MasterTransfer(&SPI_PERIInstance,TxData_au8,RxData_au8,1))
{
while (false == SPI_Transfer_CompFlag);
return RxData_au8;
}
}
void SPI1_TxRxTransferCompleteCB(void *driverState, spi_event_t event, void *userData)
{
SPI_Transfer_CompFlag = true;
}
The reason for using SPI_MasterTransfer() as a blocking call since it not using any RTOS functions, as you see in my code snippet it is working fine as expected when I set priority to 0 and for other priorities(default or 1) it won't coming to call back function.
below are the screen shots of the NVIC registers which says other interrupts are not set yet.
Sorry to keep you waiting!
I was on vacation recently and just back to the office.
Have you check the value of Interrupt Priority Register?
INT_SYS_SetPriority(LPSPI1_IRQn, 1); I can see the value be set in Interrupt Priority Register of LPSPI1.
Would you please attached the simplified test program? So that I can test directly.
I am not able to reproduce this issue with example project. But this happens with actual project that we are working on.
Below are content of SPI register and NVIC registers. SPI register have Interrupt enabled, and from NVIC as well, it is evident that interrupt (LPSPI1 i.e. IRQ 27 is pending) but still IRQ handler isnt invoked.
SPI Registers:
Since the IER register content has interrupts enabled, as SR also indicates TDF bit set, which should trigger IRQ, but that doesnt happen, no clue why.
Status of NVIC registers at this point:
As shown below, IRQ 27 is enabled and is pending.
Priority Registers:
Please check if you configure the BASEPRI
If you can send your project to me, it would be better to check issue.
BASEPRI is not configured. Sharing the project may not be possible.
Have you tried to use SPI_MasterTransferBlocking? This function initializes a blocking master transfer with time-out.
