@Robin_Shen
I am not able to reproduce this issue with example project. But this happens with actual project that we are working on.
Below are content of SPI register and NVIC registers. SPI register have Interrupt enabled, and from NVIC as well, it is evident that interrupt (LPSPI1 i.e. IRQ 27 is pending) but still IRQ handler isnt invoked.
SPI Registers:
Vijay_Arwapally_0-1613642226113.png
Since the IER register content has interrupts enabled, as SR also indicates TDF bit set, which should trigger IRQ, but that doesnt happen, no clue why.
Status of NVIC registers at this point:
As shown below, IRQ 27 is enabled and is pending.
Vijay_Arwapally_1-1613642328529.png
Priority Registers:
Vijay_Arwapally_2-1613642389154.png
Vijay_Arwapally_3-1613642405380.png
Vijay_Arwapally_4-1613642418507.png
Vijay_Arwapally_5-1613642437424.png
Vijay_Arwapally_6-1613642448369.png