S32K11x PORTA PIN2 interrupt

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S32K11x PORTA PIN2 interrupt

957件の閲覧回数
shindeu66
Contributor III

ipr.JPGHello,

Mr. Daniel,

I have to configure for PORTA PIN 2 of s32k116, but it is not wake up through that port pin pressing.

Also in structure for NVIC max allowed index is 8 but in DMA_Interrupt_Mapping excel it mentioned 9.

Please tell me how to do it?

Regards,s32kDMA.JPG

Shinde Umesh

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823件の閲覧回数
danielmartynek
NXP TechSupport
NXP TechSupport

Hello shindeu66@gmail.com,

On the S32K11x derivatives, there are single ISER, ICER, ISPR, ICPR registers and eight IPR registers.

To enable the PORTA interrupt, you need to set the 9th bit of the ISER register.

S32_NVIC->ISER[0] |= (1 << 9);‍‍‍

pastedImage_3.png

Then, you can set its priority in the IRQ1 bit-field of the IPR2 register.

S32_NVIC->IPR[2] |= S32_NVIC_IPR_PRI_1(0b01000000);  // Priority level 1‍‍

As you can see below, there are only four priority levels.

pastedImage_4.png

If the interrupt does not work in RUN, please share a test project.

Thank you,

BR, Daniel

823件の閲覧回数
shindeu66
Contributor III

Hello,

Mr. daniel

I am sending you a sample project in the attachment.

The functionality I want to design is when switch PTA1 is detected mcu should go to VLPS mode.

after entering VLPS if PTA2 is detected mcu should come back to normal run mode.

please have look and tell me the changes required.

Regards,

Shinde Umesh

https://drive.google.com/open?id=1wo5sQhsZhAzqZ9E4AHkUnb4utiz79DxRlowpoerrhttps://drive.google.com/open?id=1wo5sQhsZhAzqZ9E4AHkUnb4utiz79DxRvlps.JPG

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823件の閲覧回数
danielmartynek
NXP TechSupport
NXP TechSupport

Hello shindeu66@gmail.com,

Could you please test each function separately? 

  • PTA Interrupt
  • Transition to VLPS
  • PTA wakeup

I haven't tested the code but I see a few things: 

  • Why do you disable interrupts just before the MCU goes to VLPS?
  • As discussed here: S32K148 - switching between RUN and VLPS, don't use the Sleep-on-exit mode if you don't want the application to go back to VLPS again after the wake-up ISR. 

Regards,

Daniel