S32K can't wake up from VLPS occasionally

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S32K can't wake up from VLPS occasionally

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wwww
Contributor II

hi,

    i"m using the s32k142 with RUN mode and VLPS mode, through the GPIO interrupt to wake up the chip from VLPS mode, it's working fine in most of times,but there is a slight chance that can't wake up from VLPS mode,only reconnect the power can make chip normal.this situation happened in different boards and can't reproduce.

    I would like to know,what situation may cause the MCU can't wake up from VLPS mode? thank you very much.

BR

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi,

Could you please make sure that PREDIV_SYS_CLK frequency / BUS_CLK frequency configuration for RUN/VLPR mode is greater than or equal to 2 before executing the transition to VLPS.

Mask Set Errata for Mask 0N33V

https://www.nxp.com/docs/en/errata/S32K142_0N33V.pdf 

ERR011063

Thank you,

BR, Daniel

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi,

Please make sure that the interrupts are not masked when the MCU enters VLPS.

You could try using the highest interrupt priority only for the interrupts that are used to wake the MCU up.

BR, Daniel

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wwww
Contributor II

hi,

    we enabled the PORTB interrupts before enters VLPS, the wake up source was connected with PTB ,the priority was highest.

    and , it can wake up normally at the most of times,just 2 or 3 times dead in VLPS. 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi,

Could you please make sure that PREDIV_SYS_CLK frequency / BUS_CLK frequency configuration for RUN/VLPR mode is greater than or equal to 2 before executing the transition to VLPS.

Mask Set Errata for Mask 0N33V

https://www.nxp.com/docs/en/errata/S32K142_0N33V.pdf 

ERR011063

Thank you,

BR, Daniel

1,851件の閲覧回数
wwww
Contributor II

Hi Daniel,

 I checked my clock configuration and maybe it's the reason.pastedImage_3.png

and I was wondering whether there should be some inconsistency about the data in the example. Based on the errata, the dividers in red circles should not be the same but parameters is the same. 

pastedImage_1.png

thank you !

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi,

Yes, based on the RM, SCG_RCCR[DIVBUS] = 0b0001 divides the clock by 2.

Thank you for reporting it.

pastedImage_1.png

Regards,

Daniel

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