S32K TRGMUX I don't understand trgmux_in0~trgmux_in10

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S32K TRGMUX I don't understand trgmux_in0~trgmux_in10

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LijieDu
Contributor II

LijieDu_0-1692434035858.png

As shown in the above figure, I don't quite understand trgmux_in0~in10 and trgmux_out0~out10.

Does anyone can provide some docs to learn?

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Senlent
NXP TechSupport
NXP TechSupport

Hi@LijieDu

you need to read S32K-RM -> Chapter 19 Trigger MUX Control (TRGMUX) for more detail.

Senlent_3-1692507958330.png

Senlent_4-1692508062175.png

 

 

 

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Senlent
NXP TechSupport
NXP TechSupport

Hi@LijieDu

you need to read S32K-RM -> Chapter 19 Trigger MUX Control (TRGMUX) for more detail.

Senlent_3-1692507958330.png

Senlent_4-1692508062175.png

 

 

 

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LijieDu
Contributor II

@Senlent Thanks!

But I still don't know how to make the trgmux_in4 as a valid signal to trigger lpit ch0.

 

 

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Senlent
NXP TechSupport
NXP TechSupport

Hi@LijieDu

There are the following routines in the IDE, you can refer to this routine for modification, this is very simple, almost no need for users to modify the code

Senlent_0-1692626030928.png

Senlent_1-1692626416839.png

 

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LijieDu
Contributor II

@Senlent Thanks!

I Saw it yesterday, and it run as you said.

Also, when I  shorted PTD3 to 5V, the lpit ch0 interrupt will also be triggered, So trgmux_in4 is enabled when there is a rising edge on the pin PTD3, right?

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Senlent
NXP TechSupport
NXP TechSupport
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