S32K MPU implementation to realize the SW partition

[joan_ni]

Hi , Team 

      we are using the NXP S32K144/146 chips in our design, when implementation the SW partition to isolated the ASIL and QM memory and tasks using MPU  

As the description in the reference manual, we have 3 ways to realize the partition, but in our application , we only have one master (Core), the usable method are TIP2 and TIP 3; 

TIP 2:  change the user/supervisor mode 

TIP 3: dynamic change the access right .

what is suggest way to realize the SW partition ? and if possible , please also help to list the disadvantages of each methods 

or if you have better way to use MPU, please let us know , thank you very much ~~

Joan

[lukaszadrapa]

Hi Joan,

there's one more option which can be used for this purpose - Process ID (PID) which is also mentioned in the table you shared.

Let me share some screenshots from the reference manual:

And Region Descriptor n, Word 3 (RGD1_WORD3 - RGD15_WORD3):

And for reference only - I wrote simple example for MPC5748G which shows how PID works:

https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5748G-SMPU-initialization-Process-ID-...

It's different device, different MPU but I'm sharing it to see the principle. Just see the test case in main function.

Regards,

Lukas

[joan_ni]

Hi, @lukaszadrapa 

     thanks for your support, actually we research with the PID register, but it can not implement our application. For each region, the assess right (R/W/X) is defined according to the region descriptor register. 

Region 0;(Same region)

PID 1 (allow) can visit the region , PID 2 can not visit the region, this can easy realized.  

but we want realize below condition

For region0, Process 1 have the assess right (R/X/W), but Process 2 have the assess right (R)[read only ], how to realize this function ?  or do you have better solution ? 

the solution what we have is list as beginning, so we want know if we do like this , is there any side-effect ? 

Hoping reply form your side.  

Joan  

[lukaszadrapa · Accepted solution]

You can do that with PID. The idea is following: you will configure two descriptors covering the same region. You will also enable the PID in both descriptors, so these descriptors are not considered as overlapping because also PID will be used to check if there's a hit or not. So, you can configure access rights for each process ID separately.

Regards,

Lukas

[joan_ni]

Hi, @lukaszadrapa 

     As my understanding , according your solution we should dynamic change MCM_PID content.

we have descriptor 1(With PID 1,r/w/x) and descriptor 2(with PID 2,r). and when executing task1 set MCM_PID=1,  and executing task 2 MCM_PID=2, like this for the same region we can have different assess right. If there is something wrong, please let me know .

but how to understand ''System software loads this register before passing control to a given user mode
process.'' this words in RM, if the interrupt comes, (with supervisor assess right ,like PendSV)  also need setting the PID ? 

or PID only used in user mode ?

another problem is when in task1 , a interrupt happened , will the interrupt still using the same assess right with Task 1?  and when the interrupt finished, back to task1, how to judgement the assess right ? 

if you have better solution, please share with us , thank you ~~

Joan 

[lukaszadrapa]

Hi Joan,

I'm sorry for late response.

PID takes effect in both user and supervisor mode.

The best option is to have ISR handlers in another part of flash memory which is covered by separate descriptor. Then just disable PID for this descriptor, so it doesn't matter what the current state of MCM_PID is. When you come back from interrupt, the MCM_PID and access rights will be still valid.

Regards

Lukas

[joan_ni]

Hi, @lukaszadrapa

i am waiting for your reply, Can you share us with some suggestions ,thank you very much ~~

Joan  

[joan_ni]

@lukaszadrapa 

Great thanks , it make sense ~~

Joan