RTC TPR not constant after initialization of RTC with SOSC

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RTC TPR not constant after initialization of RTC with SOSC

632 Views
Campino
Contributor I

Hello guys, this is my first post here and i'm not that experienced as well so please be patient with me.

I'm working on a project right now where i'm trying to get the internal RTC of an S32K144UAVLL working to get accurate timestamps in milli- and microseconds for debugging. I've chosen the SOSC as input for the ticks.

Right now I'm initialising the SOSC with the following config in the "clockmanager.c":

 
 

 

...
  {
        .clockName = RTC0_CLK,
        .clkGate = true,
        .clksrc=CLK_SRC_SOSC_DIV1,
        .frac = MULTIPLY_BY_ONE,
        .divider = DIVIDE_BY_ONE,
    },
...
clock_manager_user_config_t clockManager_InitConfig0 = {

    .scgConfig =
        {
            .rtcConfig =
                {
                    .initialize = true, /*!< Initialize  */
                    .rtcClkInFreq = 0U, /*!< RTC_CLKIN   */
                },
            .soscConfig =
                {
                    .initialize = false,      /*!< Initialize or not the System OSC module.                 */
                    .freq = 25000000U,        /*!< System OSC frequency.                                    */
                    .enableInLowPower = true, /*!< System OSC is enable or not in low power mode.           */
                    .enableInStop = false,    /*!< System OSC is enable or not in stop mode.                */
                    .monitorMode = SCG_SOSC_MONITOR_DISABLE, /*!< System OSC Clock monitor mode.            */
                    .locked = false,                   /*!< System OSC Control Register can be written.          */
                    .range = SCG_SOSC_RANGE_HIGH,      /*!< System OSC frequency range.                          */
                    .gain = SCG_SOSC_GAIN_HIGH,        /*!< System OSC high-gain operation.                      */
                    .div1 = SCG_ASYNC_CLOCK_DIV_BY_64, /*!< Asynchronous peripheral source.                      */
                    .div2 = SCG_ASYNC_CLOCK_DIV_BY_1,  /*!< Asynchronous peripheral source.                      */
                    .extRef = SCG_SOSC_REF_OSC,        /*!< System OSC External Reference Select.                */

                },

 

 
also I'm doing this after the initialization  :
 

 

void rtc_init(uint32 instanceId, const rtc_config_t *rtc_config)
{
    LPTMR_DRV_Init(instanceId, (lptmr_config_t *)rtc_config, 1);

    // Disable the RTC time counter
    RTC->SR &= ~RTC_SR_TCE_MASK;

    // Set the initial value of the time counter
    RTC->TSR = 0;

    // Enable the RTC alarm interrupt
    RTC->IER |= RTC_IER_TAIE_MASK;

    // Set the target value for the RTC alarm interrupt
    RTC->TAR = RTC->TSR + 10; // Interrupt after 2 seconds}

    // Enable the RTC time counter
    RTC->SR |= RTC_SR_TCE_MASK;
}

 

 
Following things are occurring If I'm trying to read the registers:
If I'm looking at the TSR and the TPR registers the TSR is counting up, so far so good, but the TPR has no constant value so the prescaling does not work correctly - right? Is there anything I'm missing?
If you need more information, just tell me, I'm trying to provide as good as possible.
 
Thanks in advance,
Campino
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VaneB
NXP TechSupport
NXP TechSupport

Hi @Campino 

When the time counter is enabled, the TPR is read-only and increments every 32.768 kHz clock cycle. When SR[TOF] or SR[TIF] are set, the time counter will read as zero. When the time counter is disabled, the TPR can be read or written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic
one to a logic zero.

Regarding TSR, writing with zero is supported but not recommended because TSR will read as zero when SR[TIF] or SR[TOF] are set (indicating the time is invalid).

Also, did you already test the SDK's RTC example?

 

B.R.

VaneB

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Campino
Contributor I

Hi @VaneB,

thank you, I just came back from vacation and I'm going to test the example, also the information helped me a lot.

K.R.

Campino

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