LPUART Tx not tristating when transmitter disabled

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LPUART Tx not tristating when transmitter disabled

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Joey_van_Hummel
Contributor IV

Hi;

We have an issue with an S32K146 (0N73V) with the Tx-pin not going into tri-state after CTRL[TE] is disabled. According to Ref. Man. rev. 14:

When TE is cleared, this register bit reads as 1 until the transmitter has completed the current character and the TXD pin is tristated.

We observe non-conformant behaviour. When CTRL[TE] is disabled:

  • If CTRL[TXINV] = 0, TXD is forced high.
  • If CTRL[TXINV] = 1, TXD is forced low.

In other words, LPUART forces TXD to the idle state when the transmitter is disabled, in contrast to what the RM suggests.

I've confirmed that during this behaviour, CTRL[TE] is low. PORT MUX is correctly set to LPUART (Which the CTRL[TXINV] effect confirms) and Pull-devices are disabled.

Did I misunderstand the RM or is something else going on?

Kind regards,

Joey

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VaneB
NXP TechSupport
NXP TechSupport

Hi @Joey_van_Hummel 

Just to ensure, the TXD is tristated in single-wire mode as long as the transmitter is disabled or the transmit direction is set to receive data. Do you meet these conditions?

 

B.R.

VaneB

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VaneB
NXP TechSupport
NXP TechSupport

Hi @Joey_van_Hummel 

Just to ensure, the TXD is tristated in single-wire mode as long as the transmitter is disabled or the transmit direction is set to receive data. Do you meet these conditions?

 

B.R.

VaneB

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Joey_van_Hummel
Contributor IV

Hi @VaneB, thanks for your reply.

I wasn't aware that tristate applies only to single-wire mode. I do now see a mention of tristating in single-wire mode under 53.2.3, but the conditions under "normal" operation are left undefined.

I am used to S12 devices where TXD is high-impedance when the transmitter is disabled. The observed behaviour in the S32 is not explicitly described in the RM as far as I can see, and the description for CTRL[TE] does unconditionally state that it will tristate. Hence my confusion.

If that's the case, in my opinion it would be good to add an explicit description of the pin state when TE is 0 under normal operation, to avoid ambiguity.

Kind regards,

Joey

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VaneB
NXP TechSupport
NXP TechSupport

Hi @Joey_van_Hummel 

Thanks for the feedback.
I will inform the corresponding team.

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Joey_van_Hummel
Contributor IV

Thank you for your time, I've accepted your original reply as a solution since it answers my question.

Kind regards,

Joey

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