dear guys:
I want to erase and write the sector, but I meet a problem after doing the erase. first of all I copy the flash_drv code into ram.
1. I try to erase 00420000 and the length is 2K for example(in fact I will erase the 8*8K length)
2. I unlock the bit2 of SSPELOCK[0] because this address is located in block0 of S32K312
3. I write the address 0x00420000 into PFCPGM_PEADR_L
4. I Set the IP_FLASH->DATA[0] as 0xFFFFFFFF which I do not know whether it is necesarry becasue I do not find this action in usermanul
5. I set the bit of ERS in MCR register
in fact , I meet the PES bit setting in MCRS in the watch windows after executing the step4 and I also meet the PES bit setting after step5 if I mark the step4.
colud you pls help me .thank you
已解决! 转到解答。
It might be, because the system clock configuration must be set precisely to one of the clock options listed in the RM, Section 24.7.2 System clocking configurations.
Please check all the clocks and let me know.
Thank you
Hi @yinqiu,
Have a look at Figure 2. Erase sequence flow diagram
in AN13388: S32K3 Memories Guide
https://www.nxp.com/webapp/Download?colCode=AN13388
Also, you can use or refer to the RTD C40_Ip driver.
Regards,
Daniel
hi :
I check the procedure and I think the sequence is correct but I still get the PES after writing DATA[0], I attach the code below, and I find in the UM and it mentiones that the PDATA could be writable after the PEADR is updated but it has some relationship with PEID. I do not care about the PEID when writing the DATA[0], do you think it will be the reason?
It might be, because the system clock configuration must be set precisely to one of the clock options listed in the RM, Section 24.7.2 System clocking configurations.
Please check all the clocks and let me know.
Thank you