I get the PES bit setting after executing erase action in s32K312

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I get the PES bit setting after executing erase action in s32K312

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yinqiu
Contributor III

dear guys:

 I want to erase and write the sector, but I meet a problem after doing the erase. first of all I copy the flash_drv code into ram.

1. I try to erase 00420000 and the length is 2K for example(in fact I will erase the 8*8K length)

2. I unlock the bit2 of SSPELOCK[0] because this address is located in block0 of S32K312

3. I write the address 0x00420000 into PFCPGM_PEADR_L

4. I Set the IP_FLASH->DATA[0] as 0xFFFFFFFF which I do not know whether it is necesarry becasue I do not find this action in usermanul

5. I set the bit of ERS in MCR register

in fact , I meet the PES bit setting in MCRS in the watch windows after executing the step4 and I also meet the PES bit setting after step5 if I mark the step4.

colud you pls help me .thank you 

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danielmartynek
NXP TechSupport
NXP TechSupport

It might be, because the system clock configuration must be set precisely to one of the clock options listed in the RM, Section 24.7.2 System clocking configurations.

Please check all the clocks and let me know.

 

Thank you

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @yinqiu,

Have a look at Figure 2. Erase sequence flow diagram

in AN13388: S32K3 Memories Guide

https://www.nxp.com/webapp/Download?colCode=AN13388

 

Also, you can use or refer to the RTD C40_Ip driver.

 

Regards,

Daniel

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yinqiu
Contributor III

hi danielmartnet:

thanks you for your reply.

I checked the Figure 2. and I have a little confused about the "start Domain Id = 1", Should I write some register for the domain ID?

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danielmartynek
NXP TechSupport
NXP TechSupport

In Figure 2, the ID is just an example

This is done by the Master/Domain writting to the PEADR register.

danielmartynek_0-1722248388321.png

 

Regards,

Daniel

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yinqiu
Contributor III

hi :

I check the procedure and I think the sequence is correct but I still get the PES after writing DATA[0], I attach the code below, and I find in the UM and it mentiones that the PDATA could be writable after the PEADR is updated but it has some relationship with PEID. I do not care about the PEID when writing the DATA[0], do you think it will be the reason?

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @yinqiu,

I don't see any code attached.

Can you send a whole test project?

 

Thank you

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yinqiu
Contributor III

Hi 

Because of the security policy of the company.I Upload the file by cellphone 

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danielmartynek
NXP TechSupport
NXP TechSupport

Please use the C40_IP RTD driver for your reference.

There are C40_Ip examples.

You can step through it and check the registers.

 

Regards,

Daniel

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634件の閲覧回数
yinqiu
Contributor III

hi 

if I erase flash before function "MCU_InitClock",it woks OK, if the erase function is called after the function "MCU_InitClock", PES comes out. is there any connection?

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danielmartynek
NXP TechSupport
NXP TechSupport

It might be, because the system clock configuration must be set precisely to one of the clock options listed in the RM, Section 24.7.2 System clocking configurations.

Please check all the clocks and let me know.

 

Thank you