Can the S32K312 chip support setting the ITCM RAM as system RAM?

[mikesteven]

Hi, NXP team:

    The current project is using the S32K312 chip. The SRAM is not sufficient for our needs, and the DTCM is being used to store data. However, the ITCM is not being used yet. I would like to know if this chip supports using the ITCM for system storage. If it does, how should it be configured?

[lukaszadrapa]

Hi @mikesteven 

yes, ITCM can be used for data storage. No configuration is required, the ITCM must be only initialized due to ECC which is already done in startup files.

Regards,

Lukas

[luhaiou_autolink]

Hello, I have a question that I need to ask. About ITCM, DTCM, MPU Access permission field settings

ITCM and DTCM are the same, but different from SRAM，

Do I need to adjust ITCM and DTCM permissions? How to modify it?

FreeRTOS is used in the project,Is there anything to be aware of?

[mikesteven]

Hi, @lukaszadrapa :

Thanks for your reply!

Could you give me a sample code which tell me how to initialize ITCM?

[lukaszadrapa]

Here is a piece of code copied from startup_cm7.s:

ITCM_Init:
/* Initialize ITCM ECC */
ldr r0, =__ITCM_INIT
cmp r0, 0
/* Skip if __TCM_INIT is not set */
beq ITCM_LOOP_END

ldr r1, =__INT_ITCM_START
ldr r2, =__INT_ITCM_END

subs r2, r1
subs r2, #1
ble ITCM_LOOP_END

movs r0, 0
movs r3, 0
ITCM_LOOP:
stm r1!, {r0,r3}
subs r2, #8
bge ITCM_LOOP
ITCM_LOOP_END:

And now I can see that some initialization is really required, I didn't notice that before. It is implemented/fixed in RTD 3.0.0. Earlier versions didn't do that:

From the same file:

/* Enable TCM and Disable RETEN bit */
LDR r1, =CM7_DTCMCR
LDR r0, [r1]
bic r0, r0, #0x4
orr r0, r0, #0x1
str r0, [r1]
/* Enable TCM and Disable RETEN bit */
LDR r1, =CM7_ITCMCR
LDR r0, [r1]
bic r0, r0, #0x4
orr r0, r0, #0x1
str r0, [r1]

ITCM is enabled by default but RETEN must be cleared as described in S32K3 RM:

Regards,

Lukas

[mikesteven]

Hi, @lukaszadrapa :

Thank you for your reply and I apologize for the delay in my response.

I checked my startup code and found that the corresponding snippet inside is basically consistent with the one you provided.

In my LD script file, corresponding intervals have been defined to store data. At the same time, I also placed the corresponding address in the initialization data structure

However, when I put two variables into ITCM during the task, the program cannot run. I used Lauterbach to check the error status register and found that the BFSR ->IMPRECISERR bit was set. Does this mean my code is incorrect?

Regards,

Mike

[lukaszadrapa]

If you check the ITCM by debugger, can you see if the ITCM is initialized (due to ECC) and if the variables are initialized?

Regards,

Lukas

[mikesteven]

Thanks for your reply!

I have listened to your suggestion and checked the initialization of ITCM RAM. I confirm that ITCM has been initialized. Some of the variables I use are declared in functions and may be used for queue operations, so they may not have been initialized when declared. But I placed it in the bss section, and when the MCU starts, the corresponding memory will be initialized to 0.

After debugging, I found that when the first linked data on ITCM is a variable, the program can run normally. However, when this data is an array or pointer (some code will null the address), the program will throw an exception. I think this is because the first address of ITCM is 0. Therefore, I isolated the first 4 bytes of ITCM. And the code that was originally unable to run can run normally.

Moreover, I found that when the 0 address is a variable, the address of this variable cannot be seen in the debugger, and its value cannot be seen either. So I guess this is also due to the 0 address?

Regards,

Mike

[lukaszadrapa]

Hi @mikesteven 

I'm sorry for delayed response.

Which compiler do you use? I can remember I tried this some time ago with GCC in S32DS and it worked - I could write the ITCM at 0x0 via pointer. So, I guess it could be related to compiler you use.

Regards,

Lukas

[mikesteven]

Hi, @lukaszadrapa 

Thanks for you reply again!

The compiler which I used follows as below picture:

In addition, I have a supplement that there will be some assertions in my code, such as pointer null. Just like this,

When the assertion fails, the program enters a dead loop, which may cause the program to enter an exception in FreeRTOS.

[lukaszadrapa · Accepted solution]

Well, after some testing, I can  see it's caused by optimizations. If optimization level is set to none or to -O1, it is translated in the right way. If other optimization levels are used, it does not work. I can see two quick workarounds:

1. Shift the start of ITCM in linker file a little bit, so zero address is not used.

2. Set optimization level to none or to -O1.

The first workaround is better solution, I think.

Regards,

Lukas

[cg11]

Hi， I Set optimization level to -O2. I want to Shift the start of ITCM in linker file a little bit, then zero address is not used, but how to solve this issue "Break at address "0x0" with no debug information available, or outside of program code."

[Chris-Sun]

Hi @cg11 

Why are both parameters ORIGIN configured as 0x00002000 for int_itcm0 and int_itcm ?

[mikesteven]

Hi, @lukaszadrapa 

Yes, the first plan is also the one I am currently using. Thank you for your answer!

Regards,

Mike