S32K ナレッジベース

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******************************************************************************** Detailed Description: This example shows the use of SRAM retention after SW reset. The SW reset is triggered by pressing the SW3 button on the S32K144 EVB The reset is delayed in RCM module: 514 LPO cycles. In the RCM interrupt, SRAMU_RETEN and SRAML_RETEN are cleared allowing to retain SRAM data during the reset. After software reset, SRAMU_RETEN and SRAML_RETEN are set to1 to allow accesses to SRAM. During software initialization in the startup_S32K144.S, ECC RAM initialization is skipped. After that, we can check the written data before reset are still placed in the SRAM. ------------------------------------------------------------------------------ Test HW: S32K144EVB-Q100 MCU: S32K 0N57U Debugger: S32DSR1 ********************************************************************************

******************************************************************************************************** Detailed Description: On WDOG timeout, the WDOG module requests reset in the Reset Control Module (RCM). The reset request to RCM can be delayed by 128 bus clock cycles if the WDOG interrupt is enabled (WDOG_CS[INT] = 1). If enabled, the WDOG interrupt vector is fetched or it becomes pending in NVIC. After the delay, the reset is requested in RCM. Independently of the WDOG interrupt, the RCM can again delay the reset by up to 514 LPO additional clock cycles if the corresponding RCM_WDOG interrupt is enabled (RCM_SRIE[GIE, WDOG] = 1). If so, instead of forcing reset immediately, the module requests the RCM interrupt in NVIC and forces the reset after the additional delay (RCM_SRIE[DELAY]). Either way, the reset is forced, it can’t be stopped only delayed. This example enables the WDOG interrupt in the WDOG_CS register but leaves this interrupt disabled in NVIC. That means that this interrupt becomes pending in NVIC on the WDOG timeout, it sets the WDOG_CS_FLG, but the vector doesn’t get fetched. The RCM interrupt is enabled and it gets asserted in NVIC after the WDOG interrupt delay (2.67us (48MHz BUS CLK)). The WDOG flag (WDOG_CS_FLG) is read in the RCM ISR instead. The execution stays in an infinite loop for 514 LPO (128kHz) cycles (~ 4ms) until the reset is forced. ------------------------------------------------------------------------------------------------------------------------- Test HW: S32K144EVB-Q100 MCU: S32K144 0N57U Debugger: S32DSR1 OpenSDA Target: internal_FLASH ********************************************************************************************************

******************************************************************************** * Detailed Description: * RAM self-test is performed after reset in startup_S32K144.s file. * The RAM self-test should be executed right after reset, so it does not destroy * data loaded to RAM by init functions. The code is inserted after * initialization of core registers. RAM initialization is commented out because * the same operation is done by the self-test. * The test flow is: * 1. Write pattern 0x55AA55AA to first word in RAM * 2. Read the data back * 3. Compare the data and increment error counter if not equal * 4. Write inverse pattern 0xAA55AA55 to first word in RAM * 5. Read the data back * 6. Compare the data and increment error counter if not equal * 7. Clear the first word in RAM to leave whole RAM erased to ‘0’ at the end of test * This procedure is repeated for whole RAM. * If the error counter is different from zero at the end, the program stays in * endless loop until watchdog reset. * * ------------------------------------------------------------------------------ * Test HW: S32K144EVB-Q100 * MCU: FS32K144UAVLL 0N57U * Fsys: Default * Debugger: Lauterbach Trace32 * Target: internal_FLASH * ********************************************************************************

******************************************************************************** Detailed Description: Configures the FlexCAN 0 to transmit and receive message into RXFIFO. LOOPBACK mode is enabled. Two IDs are set into RXFIFO ID table. DMA is configured to read the message from RXFIFO. Within DMA major interrupt the new message is send according to which Identifier Acceptance Filter was hit. ------------------------------------------------------------------------------ Test HW: S32K144 EVB-Q100 MCU: PS32K144HFVLL 0N77P Fsys: 160MHz Debugger: Lauterbach Target: internal_FLASH ******************************************************************************** Revision History: 1.0 Sep-4-2017 Petr Stancik Initial Version *******************************************************************************

******************************************************************************** * Detailed Description: * * This example shows how to use the back-to-back mode of the PDB to trigger * sequence of ADC channels conversion. 4 PDB channel pre-triggers/triggers are * generated upon single PDB SW trigger. The first trigger is started by the PDB, * no delay is used. Next 3 triggers start after corresponding acknowledgment is * received from ADC. * * DMA is configured to read the ADC result registers. * Within DMA major interrupt the new conversion scan is started via PDB SW request. * * Converted data is used to change color of the EVB led based on Trimmer position. * * ------------------------------------------------------------------------------ * Test HW: FRDM-S32K144 * MCU: PS32K144HFVLL 0N77P * Fsys: 160MHz * Debugger: S32DS * Target: internal_FLASH * ********************************************************************************

******************************************************************************** Detailed Description: Example shows how to use FlexCAN 0 Pretended networking mode to allow FlexCAN module to wake up MCU from STOP mode. Wake up by Timeout and wake up by Match events are enabled. Also pin interrupt can be used to exit STOP mode. So MCU enters STOP mode by pressing SW3 button. MCU exits STOP mode when one of following happens: - no CAN message comes in 8sec (CAN PN timeout event) - message with standard ID 0x554 or 0x555 comes (CAN PN match event) - SW2 button is pressed (PTC12 interrupt) In run mode blue LED is dimming and the rate is different for each wakeup event ------------------------------------------------------------------------------ Test HW: S32K144 EVB-Q100 MCU: FS32K144UAVLL 0N57U Fsys: 160MHz Debugger: Lauterbach, OpenSDA Target: internal_FLASH ********************************************************************************

****************************************************************************************************************** Detailed Description: The example code shows CMP in Round-robin mode. CMP is clocked (125kHz) and triggered (80ms) by LPTMR, operates in VLPS. Input channels are CMP0_IN1 (PTA1), CMP0_IN2 (PTC4), CMP0_IN3 (PTE8), CMP0_IN4 (PTC3). The initial state of CMP outputs is 0 (Input analog pins < DAC input (Vin1/2)) The input pins are pulled down internally for debugging purposes. CPM will wake up the MCU if an input has changed. BLUE LED flashes 1x if CMP_IN1 has changed, 2x CMP0_IN2, 3x CMP0_IN3, 4x CMP0_IN4. After that, the MCU goes back to VLPS. ------------------------------------------------------------------------------------------------------------------------------------- Test HW: S32144EVB-Q100X MCU: S32K144 (0N47T) Debugger: S32DS2.0, OpenSDA Target: internal_FLASH ******************************************************************************************************************

特集記事

The S32K3 family of 32-bit AEC-Q100 qualified MCUs combines a scalable family of Arm® Cortex-M7-based microcontrollers built on long-lasting features with a comprehensive suite of production-grade tools. S32K3 MCUs are included in NXP’s Product Longevity Program, guaranteeing a minimum of 15 years of assured supply. The S32K3 offers dedicated peripherals set for rapid motor control loop implementation: enhanced Modular IO Subsystem(eMIOS), Logic Control Unit (LCU), TRGMUX, BodyCross-triggering Unit (BCTU), Analog to Digital Converter(ADC), and Analog Comparator (CMP). The comprehensive motor control ecosystem based on Automotive Math and Motor Control Library(AMMCLib) set, FreeMASTER with Motor Control ApplicationTuning (MCAT) tool and Model-Based Design Toolbox (MBDT) helps to enable S32K3 MCU in wide range of motor control use cases. The table below points to the articles with more detailed description each of S32K3 motor control use cases, hardware description, links to appropriate application notes and their addendums, and software repositories. Device HW Article S32K344 MCSPTE1AK344 12 V development kit engineered for 3-phase PMSM and BLDC motor control applications FOC with dual shunt current measurement Article focuses on solution based Field Oriented Control (FOC) technique (typically used for 3-phase PMSM motors) with dual shunt current measurement and without any position sensor (sensorless). The Encoder sensor is supported by SW option, but missing on HW kit. The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with high-level Autosar complient API or low-level non-Autosar API. FOC with single shunt current measurement Article focuses on solution based Field Oriented Control (FOC) technique (typically used for 3-phase PMSM motors) with single shunt current measurement and without any position sensor (sensorless). The Encoder sensor is supported by SW option, but missing on HW kit. The single shunt current measurement is advanced technique that allows decrese the cost of Bill of Material (BOM). The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with high-level Autosar complient API or low-level non-Autosar API. FOC integrated with FreeRTOS Article focuses on integration of motor control software (based on FOC with dual shunt current measurement) and Real Time Operating System (FreeRTOS). The available example code is based ANSI-C code and uses RTD drivers with low-level non-Autosar API. Six-step commutation control. Article focuses on solution based Six-step commutation (6-step) technique (typically used for 3-phase BLDC motors) with Hall position sensor and without any position sensor (sensorless). The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with low-level non-Autosar API. Note: the list of use cases cannot cover all combinations of MCU, current measurement scenario, control technique and sensor inputs, but should work as a base reference for most common configurations. This list is not final, please follow this acticle to be notified about updates with new use cases.

S32K ナレッジベース

S32K Knowledge Base

ディスカッション

Example S32K144 RAM Retention S32DS.R1

Example S32K144 WDOG RCM interrupt

Example S32K144 RAM selftest simple S32DS 2018.R1

Example S32K144 FlexCAN0 RXFIFO DMA nonSDK S32DS13

Example S32K144 PDB ADC trigger DMA ISR S32DS

Example S32K144 FlexCAN Pretended Networking STOP mode test S32DS.ARM.2.2

Example S32K144 CMP Round-robin S32DS2.0

S32K3 Motor control SW examples