Lower frequency PWM in OPWFMB mode

[Hareesh]

Hi NXP team,

We are using S32K344 EVK board and S32 design studio 3.5..

We require a PWM frequency of 0.5 Hz for the OPWFMB mode (variable frequency and variable duty cycle),

The system clock and ADC clock will both decrease if the EMIOS module frequency is lowered to achieve lower frequency PWM because both have the same source clock (CORE_CLK) (Please refer the attached screenshot).

Is it feasible to switch the EMIOS module's clock source from CORE_CLK? If so, how should it be done?

If we set the CORE_CLK = 20 MHz,

EMIOS_CLK = 20M / 16(Clock Prescaler) = 1.25 MHz

Period [in ticks] = EMIOS_CLK / PWM in Hz

PWM in Hz = EMIOS_CLK / Period [in ticks]

PWM in Hz = 1.25 MHz / 65535 (The maximum value we can set in S32 DS IDE)

PWM in Hz = 19.07 HZ

Thus, we will only obtain a minimum PWM frequency of 19.07 Hz when we use the maximum clock prescaler and period value combinations.

In order to get a PWM frequency of 0.5 Hz in OPWFMB mode, what setups are required?

Please assist me in fixing this issue.

Best regards,

Hareesh

[PetrS]

Hi,

a 0.5Hz would be possible as well. there is also global prescaler that can be used to lower eMIOS channel clock.

eMIOS is clocked from CORE_CLK (up to 160Mhz). eMIOS divides this clock by the global prescaler (MCR[GPRE] + 1) and routes the resulting prescaled clock output to the channel internal prescaler (Cn[UCPRE] + 1). Thus channel internal counter counts (CORE_CLK/global prescaler/internal prescaler) clock.
Finally assuming channel running in e.g. OPWFMB mode, its PWM frequency is calculated as

PWM frequency = CORE_CLK / global prescaler / internal prescaler / B1

B1 is a value written to channel B register.

Refer to device RM for description of eMIOS modes.

BR, Petr