S12z 16 bit timer

[shubhangi_mahaj]

Hello all,

Currently I am exploring VLG-S12zvca evaluation board. Working on 16bit timer.

I have written a small code where I am toggling GPIO pin PP6 and varying its on and off timing by using 16 bit timer, I have set ECLK to 24 MHz. i have observed following observations and Also please find attached doc for reference.

Questions:-

1) if we increment timer counter to maximum value that is 65535 and set prescalar value to 0 , it generates 2.73msec of delay, observed at ppg, it matched with calculations as mentioned below -->

Delay time = Counter value/ Eclk/2^ prescalar value

                  = 65535/24/2^0 * 10^-6

                  = 65535/24 us

                  =2730.625 us

                  =2.73ms

  I want to know that , how much minimum delay can be generated using minimum counter value ?

2) I have checked for counter value 1,2,3,4,5 it consider as 65535 and generates 2.73msec of delay it doesn't matches with calculations o, instead I have observed 1us of delay at counter value of 6, why is it?

Sr.no.	ON time Value	Off time value	Observed ON time Value	Observed Off time Value	Calculated on(us)	Calculated off(us)
1	65535	65535	2.8ms	2.8ms	2730.625	2730.625
2	10000	65535	420us	2.76ms	416.6666667	2730.625
3	1	65535	2.76ms	2.76ms	0.041666667	2730.625
4	2	65535	2.76ms	2.76ms	0.083333333	2730.625
5	3	65535	2.76ms	2.76ms	0.125	2730.625
6	4	65535	2.76ms	2.76ms	0.166666667	2730.625
7	5	65535	2.76ms	2.76ms	0.208333333	2730.625
8	6	6	1us	1us	0.25	0.25

--> Does it mean that S12zvca internally takes 24cycles for its compiling, boot loading or any other tasks that's why it supports only 1us at counter value 6?

-->is it possible to generate a delay in nanosecond by using s12zvca ? if yes then how?

Also Find code below;-

#include <hidef.h> /* for EnableInterrupts macro */

#include "derivative.h" /* include peripheral declarations */

void main(void) {

CPMUCLKS_PLLSEL = 1;

CPMUREFDIV_REFFRQ = 1; 

CPMUREFDIV_REFDIV = 0x0;

CPMUSYNR_VCOFRQ = 0x1;

CPMUSYNR_SYNDIV = 0x5;

CPMUPOSTDIV_POSTDIV = 0x0;

CPMUOSC_OSCE = 1;

while(!CPMUIFLG_LOCK){}

CPMUIFLG = 0xFF;

ECLKCTL_NECLK=0;

  //Use PP6 as output for LED

DDRP_DDRP6 = 1;

TIM0TSCR1 = 0x90;

TIM0TSCR2 = 0x10;

TIM0TIOS_IOS0=1;

for(;;){

PTP_PTP6=1;

TIM0TC0 = TIM0TCNT + 65535 ; /* start an OC0 operation_300ms */

while(!(TIM0TFLG1 & 0x01)); /* wait for PT0 to go high */

PTP_PTP6=0;

TIM0TC0 = TIM0TCNT + 65535 ; /* start an OC0 operation_300ms */

while(!(TIM0TFLG1 & 0x01)); /* wait for PT0 to go high */

}

}

Please let me know your all valuable comments and suggestion.

Thank You,

Shubhangi Mahajan

[kef2]

PTP_PTP6=1; <-- takes few bus cycles

TIM0TC0 = TIM0TCNT + 65535 ; <-- takes few cycles as well

while(!(TIM0TFLG1 & 0x01));  <-- even this takes time

You didn't take into account these. To produce more expected results you should calculate next compare time based on previous TC0 compare setting, not based on free running TCNT. Only first compare value should be set relative to TCNT, all further compares relative to TC0. This would help not loosing time track.

Regarding missing compare with TCNT+1..TCNT+5. I don't remember what those SCRx number settings mean (wouldn't you mind using meaningful defines next time, please), I guess you are using fast flag reset. Su you read TCNT, calculate new compare setting and write it to TC0, which is probably late compared to already advanced TCNT, you reset flag and just wait for full timer overflow period. It is tricky to be on time with small delays, but timer does its task well. It is up to you to choose implicit fast flag clear mode or explicit flag clear mode, as well to provide you never miss events.