S12XEP100: reducing power consumption

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S12XEP100: reducing power consumption

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binpenghu
Contributor II

hi

      I am using the s12xep100, fbus = 40MHZ,  fosc = 8Mhz, When in the pstop mode ,its consumption is about 20ma,

      And if i reduce fbus from 40mhz to 8mhz by setting SYNR register . the current reduced to 14ma in the pstop mode .

      can i just switch off the PLL model in pstop mode  and start the PLL mode when wake up ?  I tried the PLLSEL = 0 and PLLON = 0 instructions, but it doesn't affect  the current;

      according to the AN3289 and s12xep100 datasheet, the pstop mode's consumption (API , RTI ,COM enabled, PLL off, LCP mode) is about 274uA !!

      And I have set all the unoccupied GPIO as input and pull-up or pull-down. it do reduced a little .

    

Thank you~

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iggi
NXP Employee
NXP Employee

Hello,

In the Pseudo-Stop mode, the oscillator is enabled running with the reduced amplitude. The MCU core clocks / bus clock / system clocks are disabled at the system level in CRG module as like as in the full STOP mode.

Only the real time interrupt (RTI) and watchdog (COP) – running from oscillator, API and ATD modules may be enabled  in Pseudo-Stop mode.

(In other words: there is no bus clock and there is not any signal to be monitored at ECLK pin)


If the PLLSEL bit is still set when entering Stop Mode, the S12XECRG will switch the system and core clocks to OSCCLK by clearing the PLLSEL bit. Then the S12XECRG disables the IPLL, disables the core clock and finally disables the remaining system clocks.


Some notes to be aware of:


-  it is necessary to set correct measurement range at the measurement device, otherwise there can be big measurement error if the current is measured by Ammeter. Better approach is by using a current sensor and oscilloscope in order to see current just during STOP mode period. The current can be measured with 1Ohm resistor placed between MCU and supply.
-  BDM must be disconnected during measurement. The MCU must be started by HW reset. BDM consumes additional current.
-  In order to perform correct measurements it is necessary to disconnect all possible loads from MCU.


Btw, there is the MUCts04177 errata. The workaround says:

Do not modify the PLLON bit around the STOP instruction. The clock control and power down/up sequencing is automatically done by the device CRG module. Only the system clock source selection after exit from STOP must be controlled by software (CLKSEL_PLLSEL bit) as described in the Reference Manual.

http://cache.freescale.com/files/microcontrollers/doc/errata/MSE9S12XS256_0M05M.htm


Regards,

iggi

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iggi
NXP Employee
NXP Employee

Hello,

In the Pseudo-Stop mode, the oscillator is enabled running with the reduced amplitude. The MCU core clocks / bus clock / system clocks are disabled at the system level in CRG module as like as in the full STOP mode.

Only the real time interrupt (RTI) and watchdog (COP) – running from oscillator, API and ATD modules may be enabled  in Pseudo-Stop mode.

(In other words: there is no bus clock and there is not any signal to be monitored at ECLK pin)


If the PLLSEL bit is still set when entering Stop Mode, the S12XECRG will switch the system and core clocks to OSCCLK by clearing the PLLSEL bit. Then the S12XECRG disables the IPLL, disables the core clock and finally disables the remaining system clocks.


Some notes to be aware of:


-  it is necessary to set correct measurement range at the measurement device, otherwise there can be big measurement error if the current is measured by Ammeter. Better approach is by using a current sensor and oscilloscope in order to see current just during STOP mode period. The current can be measured with 1Ohm resistor placed between MCU and supply.
-  BDM must be disconnected during measurement. The MCU must be started by HW reset. BDM consumes additional current.
-  In order to perform correct measurements it is necessary to disconnect all possible loads from MCU.


Btw, there is the MUCts04177 errata. The workaround says:

Do not modify the PLLON bit around the STOP instruction. The clock control and power down/up sequencing is automatically done by the device CRG module. Only the system clock source selection after exit from STOP must be controlled by software (CLKSEL_PLLSEL bit) as described in the Reference Manual.

http://cache.freescale.com/files/microcontrollers/doc/errata/MSE9S12XS256_0M05M.htm


Regards,

iggi

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binpenghu
Contributor II

hello iggi

           Thanks a lot!  I am very thankful for your reply.

           In a minimum system of S12XEP100, the current consumption has reached 900uA with Ammeter.  As you said ,It could be big measurement error with Ammeter or other problems.

   Another question , when entering pstop mode, how should i set these gpios to reduce consumption? (inputs or outputs?)

   According to the AN3289, output pins should be set as input in the pstop mode,  and input pins should be internally or externally pulled into a known state. (pull-up or pull-down). Am I right?

         how about SCI/SPI/MSCAN/ATD modules, the pstop mode can stop the communication ,but would these I/Os (SCIs) continue to draw current ?                         Thanks again.

Regards,

bp           

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