Hello,
In the Pseudo-Stop mode, the oscillator is enabled running with the reduced amplitude. The MCU core clocks / bus clock / system clocks are disabled at the system level in CRG module as like as in the full STOP mode.
Only the real time interrupt (RTI) and watchdog (COP) – running from oscillator, API and ATD modules may be enabled in Pseudo-Stop mode.
(In other words: there is no bus clock and there is not any signal to be monitored at ECLK pin)
If the PLLSEL bit is still set when entering Stop Mode, the S12XECRG will switch the system and core clocks to OSCCLK by clearing the PLLSEL bit. Then the S12XECRG disables the IPLL, disables the core clock and finally disables the remaining system clocks.
Some notes to be aware of:
- it is necessary to set correct measurement range at the measurement device, otherwise there can be big measurement error if the current is measured by Ammeter. Better approach is by using a current sensor and oscilloscope in order to see current just during STOP mode period. The current can be measured with 1Ohm resistor placed between MCU and supply.
- BDM must be disconnected during measurement. The MCU must be started by HW reset. BDM consumes additional current.
- In order to perform correct measurements it is necessary to disconnect all possible loads from MCU.
Btw, there is the MUCts04177 errata. The workaround says:
Do not modify the PLLON bit around the STOP instruction. The clock control and power down/up sequencing is automatically done by the device CRG module. Only the system clock source selection after exit from STOP must be controlled by software (CLKSEL_PLLSEL bit) as described in the Reference Manual.
http://cache.freescale.com/files/microcontrollers/doc/errata/MSE9S12XS256_0M05M.htm
Regards,
iggi