okay, i solved to problem - partly.
now i can configure the pwm as being center alligned and coming from one clock source with the standard PWM-Bean.
what*s to do?
in cpu.c:
set PMFCFG0 =0x7 (outputs independent, setting complementairy outputs does not work for me at the moment - maybe someone can help)
correct the pwm-period as PE miscalculates the frequency nearly by factor 2. (I am running PLL at 50MHz)
in the PWM-Channel-Bean.c files (for me pwm1.c pwm2.c and so on):
for channels 2-5: manipulate the code so that LDOKA is used entirely.
see a screenshot of my settings above.
- this pwm is configured as
- 6 independend channels being clocked by one source
- 18000kHz at 50MHz PLL
working good!