MM912J637 Lifetime Counter error

[ianwilson]

Hi all,

We are using the MM912J637.  Have been for a few years now but I think we are uncovering an old issue now.

I am finding the lifetime counter is giving a wake-up about 5% too early. I want 5 seconds but am seeing about 4.75 seconds.  The error should be better than this as the system has been running and so the ALFCLK should have a recent sync against D2DSCLK. D2DSCLK should have an accuracy better than ~1%.

I am thinking that the ALFCLK may not be synchronised against the D2DSCLK correctly.  The datasheet (V5.0 Jan 2015) is slightly confusing.

It states "the low power oscillator (LPCLK) is synchronized to the more precise D2DCLK, via the D2DSCLK signal."

But later it also states "The “Calibrated Low Power Clock” (ALFCLK) could be trimmed to the D2DCLK accuracy plus a maximum error adder of 1 LPCLK period, by internally counting the number of periods of the LPCLK (512 kHz) during a D2DSCLK period.".  (My emphasis.)

The "could" here implies to me that I may need to code something to make this happen.

But, further on again, the datasheet states that this adjustment is continuously performed during Normal mode.

The code to reload the LTC counter when it rolls over and generates an interrupt (or wakeup) is:

#define SLEEP_SECONDS (5)
#define ALFCLK_HZ (1000UL)
#define LTC_RELOAD (1UL + (0xFFFFFFFFUL - (ALFCLK_HZ * SLEEP_SECONDS)))
#define LTC_RELOAD_HI ((uint16_t)(LTC_RELOAD >> 16))
#define LTC_RELOAD_LO ((uint16_t)(LTC_RELOAD & 0xFFFF))

static void ltc_timer_reload(void)
{
     LTC_CTL = 0x8100; // b 10000001 00000000 - disable LTC
     LTC_CNT1 = LTC_RELOAD_HI;
     LTC_CNT0 = LTC_RELOAD_LO;
     LTC_CTL = 0x8181; // b 10000001 10000001 - enable LTC and its interrupt
}‍‍‍‍‍‍‍‍‍‍‍‍‍

So the LTC counter should be loaded with 0xFFFFEC78 and should then count for 0x1388 x ALFCLK before rolling over; that is 5000 (decimal) ms.

My questions are:

Q1: Is the datasheet a little confusing here?

Q2: Any thoughts on why I would see a 5% error in the LTC timeout?

Many thanks for any assistance.

Regards,

Ian

[ianwilson]

Sorry for disturbing you - the problem is fixed now.

We had a PRESC value of 0x2A00 which gives a correct D2DFCLK but an incorrect D2DSCLK.

Changing PRESC to 0x2C00 gives correct frequencies for both.

R,

Ian

[ianwilson]

Further info.  If I read back the TRIM_ALF register I am getting values of about 0x81EB. If I cool the chip a little I see it fall to 0x81E8 then slowly climb back again.

So this looks reasonable and the PRDF bit is set suggesting sync is OK.

So why the error in LTC timeout?

Have I calculated the reload value wrong?