IRQ & SPI Interrupt Priority Conflicts

[KH_SRNL]

I have an application where I am interfacing an HC9S12 chip to an IR transciever through the SPI bus (via a MAX3100 chip).  The SPI bus communicates with the MAX3100.  The MAX3100 communicates with the IR module.  The SPI data transmissions to the Max3100 are interrupt driven (SPI transmit interrupt).  I also have the receive data full interrupt on the MAX3100 enabled and the output is wired to the HC9S12 IRQ interrupt.  When data is received on the IR port, the MAX3100 initiates an interrupt on the IRQ line.  In order to clear the IRQ interrupt source (the MAX3100), I must read the MAX3100 configuration register via the SPI bus.  It appears that I can't transmit data out of the SPI bus (also interrupt driven) with the IRQ interrupt active (SPI is lower priority than IRQ).

Is there a register where I can dynamically mask the IRQ interrupt long enough to send the SPI data?  Is my understanding of what I'm seeing correct?  Any help would be appreciated. 

[kef]

See IRQCR register, IRQEN bit.

Alternatively, MAX3100 can operate at >4MHz SPi clock. That's <4us for 16bit transfer. Wouldn't it be better to use SPI in polled mode?

[KH_SRNL]

Thanks,

I initially started out in polled mode but had issues with the SS timing.  It's been a while since I wrote the routine, but I believe there was an issue with using the SPI SS line on 16 bit transfers.  I wound up rerouting the SS to a PortA pin.  After sending the second character (interrupting on transmit empty), I installed a very slight delay before toggling the SS line high again. The timing was tweaked using a scope and SPI line monitor.  In regards to polled mode,  I was concerned if another interrupt source came in during an SPI transfer it would through the timing off.  From my understanding the SPI is a native 8 bit transfer (in regards to the SS line).

Perhaps you can shed more light on an alternate way to send the SPI data in polled mode where this wouldn't be an issue.

Thanks again for your help.

Kevin

[kef]

SS line should be driven manually. You set maxim chip select low, send/receive two bytes, and finally set chip select pin high. At 4MHz this takes about 4microseconds. I don't know about timing issues with MAX3100. The only not very cosy thing about MAX3100 I remember was that after each 16-bit SPI transfer (any write config, transfer byte or just check the status), you have to check R status bit and if R==1, then you have to put received character into receive queue.

Do you have more than just single MAX3100 on same SPI bus? Well, in this case MAX3100 interrupt (IRQ) could be disabled for the time needed to perform transfers to those extra devices.